Flash memory device and method for manufacturing the same
View Patent ↗A flash memory device, and a manufacturing method thereof, having advantages of protecting sidewalls of a floating gate and a control gate and preventing a recess of an active area of a source region are provided. The method includes forming a tunneling oxide layer on an active region of a semiconductor substrate, forming a floating gate, a gate insulation layer, and a control gate on the tunneling oxide layer, forming insulation sidewall spacers on sides of the floating gate and the control gate, and removing at least portions of the tunneling oxide layer and the device isolation layer so as to expose the active region.
1. A flash memory device, comprising:
a semiconductor substrate having an active region and a device isolation region therein;
an isolation layer in the device isolation region;
a tunneling oxide layer, a floating gate, a gate insulation layer, and a control gate in the active region of the semiconductor substrate;
first and second insulation sidewall spacers at sidewalk of the floating gate and the control gate, wherein the first insulation sidewall spacer is over the active region and the second insulation sidewall spacer is over the device isolation region in a cross-section of the floating gate, the gate insulation layer, the control gate, and the insulation sidewall spacers, and a portion of the isolation layer remains below the second insulation sidewall spacer in the device isolation region; and
a common source region in a predetermined portion of the active region and the device isolation region.
2. The flash memory device of claim 1 , wherein the first and second insulation sidewall spacers comprise a single layer or a combination of layers.
3. The flash memory device of claim 2 , wherein the first and second insulation sidewall spacers comprise an oxide layer and a silicon nitride layer.
4. The flash memory device of claim 3 , wherein each of the oxide layer and the silicon nitride layer has a thickness of 180-220 Å.
5. The flash memory device of claim 1 , wherein the tunneling oxide layer has a greater width than corresponding widths of the floating gate and the control gate.
6. The flash memory device of claim 1 , wherein the portion of the isolation layer is adjacent to the common source region.
7. The flash memory device of claim 1 , wherein the substrate comprises a single crystal silicon wafer.
8. The flash memory device of claim 1 , wherein the floating gate comprises a first polysilicon layer.
9. The flash memory device of claim 8 , wherein the first polysilicon layer has a thickness of about 2500 Å.
10. The flash memory device of claim 8 , wherein the gate insulation layer is on the first polysilicon layer.
11. The flash memory device of claim 10 , wherein the gate insulation layer has an oxide layer/nitride layer/oxide layer (ONO) structure.
12. The flash memory device of claim 1 , wherein the control gate comprises a second polysilicon layer.
13. The flash memory device of claim 12 , wherein the second polysilicon layer has a thickness of about 2500 Å.
14. The flash memory device of claim 1 , further comprising an insulation layer on the semiconductor substrate and over the floating gate and the control gate.
15. The flash memory device of claim 14 , wherein the insulation layer is also over the device isolation region.
16. The flash memory device of claim 8 , wherein the first polysilicon layer is on the tunneling oxide layer.
17. The flash memory device of claim 12 , wherein the control gate is on the gate insulation layer.
18. The flash memory device of claim 12 , wherein the control gate overlaps sidewalls of the floating gate.
19. The flash memory device of claim 1 , wherein the floating gate and the control gate have a same width.