Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit
View Patent ↗To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.
1. A semiconductor device with an output circuit, the output circuit comprising:
a terminal;
a plurality of first unit buffers coupled to the terminal, each of the first unit buffers having an adjustable impedance and driving, when activated, the terminal to one of first and second logic levels with an adjusted impedance;
a first control circuit adjusting an impedance of each of the first unit buffers to represent the adjusted impedance;
a second control circuit activating selected one or ones of the first unit buffers, the selected one or ones of the first unit buffers cooperating with each other to drive the terminal to one of the first and second logic levels, and
a plurality of second unit buffers coupled to the terminal, each of the second unit buffers having an adjustable impedance and driving, when activated, the terminal to one of the first and second logic levels with an adjusted impedance, wherein:
the first control circuit further adjusts an impedance of each of the second unit buffers to represent the adjusted impedance, and
the output circuit includes a first operation mode in which selected one or ones of the second unit buffers are activated in addition to the selected one or ones of the first unit buffers by the second control circuit to drive the terminal to one of the first and second logic levels through the selected ones of the first and second unit buffers and a second operation mode in which each of the first unit buffers is deactivated and selected one or ones of the second unit buffers serve to represent an impedance at the terminal.
2. The device as claimed in claim 1 , wherein the first unit buffers are substantially equal in the adjusted impedance to each other.
3. The device as claimed in claim 1 , wherein each of the first unit buffers includes a pull-up circuit having a plurality of first transistors coupled in parallel to each other and a pull-down circuit having a plurality of second transistors coupled in parallel to each other.
4. The device as claimed in claim 3 , wherein each of the first transistors is of a first conductivity and each of the second transistors is of a second conductivity.
5. The device as claimed in claim 3 , wherein selected one or ones of the first and second transistors of each of the unit buffers are turned ON to represent the adjusted impedance thereof.
6. The device as claimed in claim 3 , wherein each of first unit buffers further includes a first resistor coupled between the terminal and a first power supply line in series with the pull-up circuit and a second resistor coupled between the terminal and a second power supply line in series with the pull-down circuit.
7. The device as claimed in claim 3 , wherein at least two of the first transistors are different in ratio of a gate width to gate length from each other, and at least two of the second transistors are different in ratio of a gate width to gate length from each other.
8. The device as claimed in claim 1 , wherein the first operation mode is used to output a data signal at the terminal and the second operation mode is used for an ODT (On Die Termination).
9. The device as claimed in claim 1 , wherein the first and second unit buffers are substantially equal in the adjusted impedance to each other.
10. The device as claimed in claim 1 , each of the second unit buffers includes a pull-up circuit having a plurality of third transistors coupled in parallel to each other and a pull-down circuit having a plurality of fourth transistors coupled in parallel to each other.
11. The device as claimed in claim 10 , wherein each of the third transistors is of a first conductivity and each of the fourth transistors is of a second conductivity.