System for measuring signal path resistance for an integrated circuit tester interconnect structure
View Patent ↗Resistances of signal paths within a interconnect structure for linking input/output (I/O) ports of an integrated circuit (IC) tester to test points of an IC are measured by the IC tester itself. To do so the interconnect structure is used to link the tester's I/O ports to a similar arrangement of test points linked to one another through conductors. Drivers within the tester, which normally transmit digital test signals to IC test points via the I/O ports when the IC is under test, are modified so that they may also either transmit a constant current through the I/O ports or link the I/O ports to ground or other reference potential. The tester then transmits known currents though the signal paths interconnecting the tester's I/O ports. Existing comparators within the tester normally used to monitor the state of an IC's digital output signals are employed to measure voltage drops between the I/O ports, thereby to provide data from which resistance of signal paths within the interconnect structure may be computed.
1. A process for testing signal path resistance in a bussed signal path of an interconnect structure, wherein said interconnect structure comprises a bussed first signal path wherein said bussed first signal path provides electrical connections between a first tester connection point and a first plurality of probes disposed on said interconnect structure and said interconnect structure comprises a plurality of second signal paths wherein each second signal path provides an electrical connection between a different one of a plurality of second tester connection points and a different one of a plurality of second probes, said process comprising:
connecting the interconnect structure to a tester so that said bussed signal path is connected to a first tester input/output port and ones of the plurality of second signal paths are connected to corresponding ones of said second tester input/output ports;
providing a reference wafer comprising a plurality of separate networks, each network providing electrical interconnections between ones of a plurality of test points on said reference wafer;
bringing the plurality of probes of the interconnect structure into contact with said reference wafer so that one of said first probes is connected through one of said test points to one of said plurality of separate networks and so ones of said second probes are connected through ones of said test points to said one of said plurality of separate networks;
measuring a resistance of a portion of said bussed signal path connected to said one of said plurality of separate networks.
2. The process of claim 1 , wherein said measuring a resistance comprises:
setting a first one of said second tester input/output ports coupled to said one of said plurality of separate networks to a first voltage potential;
driving a current through said first tester input/output port;
measuring a voltage at a second one of said second tester input/output ports coupled to said one of said plurality of separate networks; and
calculating said resistance of said portion of said bussed signal path.
3. The process of claim 2 , wherein said measuring a resistance comprises:
driving a current through a first one of said second tester input/output ports coupled to said one of said plurality of separate networks;
setting a voltage potential at said first tester input/output port;
measuring a voltage at a second one of said second tester input/output ports coupled to said one of said plurality of separate networks; and
calculating said resistance of said portion of said bussed signal path.
4. The process of claim 2 , wherein said measuring a resistance comprises:
driving a current through a first one of said second tester input/output ports coupled to said one of said plurality of separate networks;
setting a voltage potential at a second one of said second tester input/output ports coupled to said one of said plurality of separate networks;
measuring a voltage potential at said first tester input/output port; and
calculating said resistance of said portion of said bussed signal path.
5. The process of claim 2 , further comprising:
bringing the plurality of probes of the interconnect structure into contact with said reference wafer so that ones of said first probes are each connected through one of said test points to a different one of said plurality of separate networks and so ones of said second probes are connected through ones of said test points to each different one of said plurality of separate networks; and
measuring resistance of each portion of said signal path connected to each different one of said plurality of separate networks.
6. The process of claim 5 , wherein said measuring resistance of each portion of said signal path comprises setting to a high impedance second tester input/output ports coupled to other ones of said plurality of separate networks.
7. The process of claim 5 , wherein said measuring resistance of each portion of said signal path is performed sequentially.
8. The process of claim 5 , further comprising verifying that said resistance of each of said portion of said signal path is within acceptable limits.
9. The process of claim 5 , wherein said measuring resistance comprises:
making a plurality of round trip path resistance measurements of said bussed signal path; and
solving for individual resistances of branches of said bussed signal path.
10. The process of claim 2 , wherein each tester input/output channel can alternatively be set to source a current, sink a current, and measure a voltage.