Methods and apparatus for translated wafer stand-in tester
View Patent ↗A translated wafer stand-in tester, being a hybrid apparatus capable of emulating the form factor and some or all behaviors of a translated wafer under test, which is operable to store, quantify, encode and convey, either directly or remotely, data from a testing system, including but not limited to pad pressure, electrical contact and temperature. The translated wafer stand-in tester may include several stacked and attached layers, at least one internal layer including electronic components operable to interact with a test system.
1. A method of determining operational characteristics of a wafer-level test system, comprising:
providing an electronic assembly suitable for testing and calibrating a wafer-level test system, the electronic assembly including a first major surface with a plurality of electrical contact terminals disposed thereon and configured to make electrical contact with a wafer-level test system;
coupling the electronic assembly to the wafer-level test system;
operating the wafer-level test system such that a plurality of signals are communicated to the electronic assembly;
processing, on the electronic assembly, the plurality of signals communicated from the wafer-level test system; and
generating on the electronic assembly one or more electrical signals indicative of the operational characteristics of the wafer-level test system;
wherein the electronic assembly comprises a substrate with a first plurality of electrical components disposed thereon; and a first stack-on layer with a second plurality of electrical components disposed thereon, the first stack-on layer disposed on the substrate;
wherein the first stack-on layer has openings therein, by means of which, uppermost portions of the first plurality of electrical components may extend through the first stack-on layer.
2. The method of claim 1 , further comprising storing, on the electronic assembly, the one or more electrical signals indicative of the operational performance of the wafer-level test system.
3. The method of claim 2 , further comprising removing the electronic assembly from the wafer-level test system; and communicating the one or more electrical signals indicative of the operational performance of the wafer-level test system to another electrical system.
4. The method of claim 1 , further comprising wirelessly transmitting, from the electronic assembly, the one or more electrical signals indicative of the operational performance of the wafer-level test system.
5. The method of claim 1 , further comprising sensing, at each of a plurality of locations on the electronic assembly, a temperature.
6. The method of claim 1 , further comprising sensing, at each of a plurality of locations on the electronic assembly, a pressure.
7. The method of claim 1 , further comprising operating a switch matrix that is disposed within the electronic assembly.
8. The method of claim 1 , wherein the thickness of the electronic assembly is substantially the same as the thickness of a wafer.
9. The method of claim 1 , wherein the thickness of the electronic assembly is substantially the same as the thickness of a wafer and a wafer translator disposed on the wafer.
10. The method of claim 1 , wherein a thermal impedance of the electronic assembly is substantially the same as a wafer under test.