Patent Assignment
Reel/Frame 035203/0773
Change of Name
Recorded: 2015-03-13
Pages: 4
Assignor
ADVANCED INQUIRY SYSTEMS, INC.
Executed: 2014-11-17
Assignee
TRANSLARITY, INC.
46575 FREMONT BLVD, FREMONT, CALIFORNIA, 94538
Covered Properties
(32)
Method and Apparatus for Wafer Scale Testing
Methods and Apparatus for Addition of Electrical Conductors to Previously Fabricated Device
Full Wafer Contacter and Applications Thereof
Methods and Apparatus for Addition of Electrical Conductors to Previously Fabricated Device
Fiber-Based Optical Alignment System
Patent:
7,379,641 →
Application:
11/799,550 →
Methods for Multi-Modal Wafer Testing Using Edge-Extended Wafer Translator
Apparatus for Full-Wafer Test and Burn-in Mechanism
Apparatus for Translated Wafer Stand-in Tester
Apparatus for Fixed-Form Multi-Planar Extension of Electrical Conductors Beyond the Margins of a Substrate
Apparatus for Providing Electrical Access to One or More Pads of the Wafer Using a Wafer Translator and a Gasket.
Methods and Apparatus for Flexible Extension of Electrical Conductors Beyond the Edges of a Substrate
Methods and Apparatus for Rotationally Accessed Tester Interface
Patent:
7,498,800 →
Application:
11/880,093 →
Methods for Access to a Plurality of Unsingulated Integrated Circuits of a Wafer Using Single-Sided Edge-Extended Wafer Translator
Wafer Translator Having a Silicon Core Isolated from Signal Paths by a Ground Plane
Fully Tested Wafers Having Bond Pads Undamaged by Probing and Applications Thereof
Wafer Translator Having Metallization Pattern Providing High Density Interdigitated Contact Pads for Component
Fiber-Based Optical Alignment System
Full-Wafer Test and Burn-in Mechanism
Chemical Removal of Oxide Layer from Chip Pads
Methods and Apparatus for Planar Extension of Electrical Conductors Beyond the Edges of a Substrate
Method and Apparatus for Single-Sided Extension of Electrical Conductors Beyond the Edges of a Substrate
Methods and Apparatus for Translated Wafer Stand-in Tester
Methods and Apparatus for Collecting Process Characterization Data After First Failure in a Group of Tested Devices
Patent:
7,786,724 →
Application:
12/427,748 →
Maintaining a Wafer/Wafer Translator Pair in an Attached State Free of a Gasket Disposed Therebetween
Methods and Apparatus for Thinning, Testing and Singulating a Semiconductor Wafer
Methods of Adding Pads and One or More Interconnect Layers to the Passivated Topside of a Wafer Including Connections to at Least a Portion of the Integrated Circuit Pads Thereon
Wafer Testing Systems and Associated Methods of Use and Manufacture
Maintaining a Wafer/Wafer Translator Pair in an Attached State Free of a Gasket Disposed
Designed Asperity Contactors, Including Nanospikes for Semiconductor Test, and Associated Systems and Methods
Application:
13/842,830 →
Publication:
US 2014/0176174
Wafer Testing System and Associated Methods of Use and Manufacture
Translators Coupleable to Opposing Surfaces of Microelectronic Substrates for Testing, and Associated Systems and Methods
Wafer Testing System and Associated Methods of Use and Manufacture
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.
Release of Security Interest
Apr 7, 2021
From: PENINSULA MASTER FUND, LTD.; PENINSULA TECHNOLOGY FUND, LP; QVT FUND LP; QUINTESSENCE FUND LP
To: ADVANCED INQUIRY SYSTEMS, INC.
Reel/Frame 055849/0609 →
Assignment of Assignor's Interest
Jan 12, 2023
From: TRANSLARITY, INC.
To: SHANGHAI CARSON SEMICONDUCTOR CO., LTD.
Reel/Frame 062357/0345 →