Methods and apparatus for planar extension of electrical conductors beyond the edges of a substrate
View Patent ↗Concurrent electrical access to the pads of integrated circuits on a wafer is provided by an edge-extended wafer translator that carries signals from one or more pads on one or more integrated circuits to contact terminals on the inquiry-side of the edge-extended wafer translator, including portions of the inquiry-side that are superjacent the wafer when the wafer and the edge-extended wafer translator are in a removably attached state, and portions of the inquiry side that reside outside a region defined by the intersection of the wafer and the edge-extended wafer translator. In a further aspect of the present invention, access to the pads of integrated circuits on a wafer is additionally provided by contact terminals in a second inquiry area located on the wafer-side of the edge-extended wafer translator in a region thereof bounded by its outer circumference and the circumference of the attached wafer.
1. A method of providing electrical access to one or more pads of one or more integrated circuits on a wafer, comprising:
providing an edge-extended wafer translator having a wafer-side and an inquiry-side, a first plurality of contact terminals disposed on a first portion of the wafer-side, a second plurality of contact terminals disposed on a second portion of the wafer-side, a third plurality of contact terminals disposed on a first portion of the inquiry-side, and a fourth plurality of contact terminals disposed on a second portion the inquiry-side;
aligning the wafer and the edge-extended wafer translator to each other; and
removably attaching the aligned wafer and edge-extended wafer translator such that the first plurality of contact terminals are in electrical contact with the one or more pads of the one or more integrated circuits;
wherein the second portion of the wafer-side is an area outside the region where the wafer is removably attached to the edge-extended wafer translator, and wherein the first plurality of contact terminals and the second plurality of contact terminals have different contact areas and different spacing therebetween;
wherein removably attaching the wafer to the wafer-side of the edge-extended wafer translator comprises creating a pressure differential between a volume defined by the space between the wafer and edge-extended wafer translator, and the atmosphere outside the defined volume.
2. The method of claim 1 , wherein each of the second plurality of contact terminals is electrically coupled to corresponding ones of the first plurality of contact terminals through wire paths internal to the edge-extended wafer translator.
3. The method of claim 2 , wherein each of the third plurality of contact terminals is electrically coupled to corresponding ones of the first plurality of contact terminals through wire paths internal to the edge-extended wafer translator.
4. The method of claim 3 , wherein each of the fourth plurality of contact terminals is electrically coupled to corresponding ones of the first plurality of contact terminals through wire paths internal to the edge-extended wafer translator.
5. The method of claim 1 , wherein the edge-extended wafer translator is D-shaped.
6. The method of claim 1 , further comprising disposing a gasket between the wafer and the edge-extended wafer translator.
7. A method of providing electrical access to one or more pads of one or more integrated circuits on a wafer, comprising:
providing an edge-extended wafer translator having a wafer-side and an inquiry-side, a first plurality of contact terminals disposed on a first portion of the wafer-side, a second plurality of contact terminals disposed on a second portion of the wafer-side, a third plurality of contact terminals disposed on a first portion of the inquiry-side, and a fourth plurality of contact terminals disposed on a second portion the inquiry-side;
aligning the wafer and the edge-extended wafer translator to each other; and
removably attaching the aligned wafer and edge-extended wafer translator such that the first plurality of contact terminals are in electrical contact with the one or more pads of the one or more integrated circuits;
wherein the second portion of the wafer-side is an area outside the region where the wafer is removably attached to the edge-extended wafer translator, and wherein the first plurality of contact terminals and the second plurality of contact terminals have different contact areas and different spacing therebetween;
wherein the wafer is removably attached to the wafer-side of the edge-extended wafer translator by a pressure differential;
wherein a gasket is disposed between the wafer and the edge-extended wafer translator.