Patent Assignment
Reel/Frame 055849/0609
Release of Security Interest
Recorded: 2021-04-07
Pages: 21
Assignors
PENINSULA MASTER FUND, LTD.
Executed: 2009-09-21
PENINSULA TECHNOLOGY FUND, LP
Executed: 2009-09-21
QVT FUND LP
Executed: 2009-09-21
QUINTESSENCE FUND LP
Executed: 2009-09-21
Assignee
ADVANCED INQUIRY SYSTEMS, INC.
20520 NW EVERGREEN PARKWAY, SUITE E 100, HILLSBORO, OREGON, 97124
Covered Properties
(44)
Desktop Wafer Analysis Station
PCT:
PCT/US2007/007866 ↗
Methods and Apparatus for Multi-Modal Wafer Testing
PCT:
PCT/US2007/013274 ↗
Method and Apparatus for Fixed-Form Multi-Planar Extension of Electrical Conductors Beyond the Margins of a Substrate
PCT:
PCT/US2007/013788 ↗
Methods and Apparatus for Planar Extension of Electrical Conductors Beyond the Edges of a Substrate
PCT:
PCT/US2007/015529 ↗
Methods and Apparatus for Flexible Extension of Electrical Conductors Beyond the Edges of a Substrate
PCT:
PCT/US2007/016379 ↗
Fully Tested Wafers Having Bond Pads Undamaged by Probing and Applications Thereof
PCT:
PCT/US2008/003858 ↗
Method and Apparatus for Wafer Scale Testing
Methods and Apparatus for Addition of Electrical Conductors to Previously Fabricated Device
Method and Apparatus for Wafer Scale Testing
Full Wafer Contacter and Applications Thereof
Methods and Apparatus for Addition of Electrical Conductors to Previously Fabricated Device
Desktop wafer analysis station
Application:
11/729,039 →
Publication:
US 2007/0229105
Fiber-Based Optical Alignment System
Patent:
7,379,641 →
Application:
11/799,550 →
Methods for Multi-Modal Wafer Testing Using Edge-Extended Wafer Translator
Apparatus for Full-Wafer Test and Burn-in Mechanism
Apparatus for Translated Wafer Stand-in Tester
Apparatus for Fixed-Form Multi-Planar Extension of Electrical Conductors Beyond the Margins of a Substrate
Laser isolation of metal over alumina underlayer and structures formed thereby
Application:
11/811,880 →
Publication:
US 2008/0003819
Apparatus for Providing Electrical Access to One or More Pads of the Wafer Using a Wafer Translator and a Gasket.
Methods and Apparatus for Flexible Extension of Electrical Conductors Beyond the Edges of a Substrate
Methods and Apparatus for Rotationally Accessed Tester Interface
Patent:
7,498,800 →
Application:
11/880,093 →
Methods for Access to a Plurality of Unsingulated Integrated Circuits of a Wafer Using Single-Sided Edge-Extended Wafer Translator
Wafer translator having a silicon core fabricated with printed circuit board manufacturing techniques
Application:
12/074,904 →
Publication:
US 2009/0224410
Wafer Translator Having a Silicon Core Isolated from Signal Paths by a Ground Plane
Fully Tested Wafers Having Bond Pads Undamaged by Probing and Applications Thereof
Wafer Translator Having Metallization Pattern Providing High Density Interdigitated Contact Pads for Component
Fiber-Based Optical Alignment System
Chemical Removal of Oxide Layer from Chip Pads
Methods and Apparatus for Planar Extension of Electrical Conductors Beyond the Edges of a Substrate
Method and Apparatus for Single-Sided Extension of Electrical Conductors Beyond the Edges of a Substrate
Wafer Prober Integrated With Full-Wafer Contacter
Application:
12/404,277 →
Publication:
US 2010/0066395
Methods and Apparatus for Collecting Process Characterization Data After First Failure in a Group of Tested Devices
Patent:
7,786,724 →
Application:
12/427,748 →
Maintaining a Wafer/Wafer Translator Pair in an Attached State Free of a Gasket Disposed Therebetween
Desktop wafer analysis station
Application:
60/786,928 →
Method and apparatus for single wafer stand-in tester
Application:
60/811,673 →
Laser isolation of metal over alumina underlayer and structures formed thereby
Application:
60/812,152 →
Method and apparatus for single sided extension of electrical conductors beyond the edges of a substrate
Application:
60/834,063 →
Method and apparatus for monolithic wafer stand-in tester
Application:
60/836,488 →
Fully tested wafers having bond pads undamaged by probing and applications thereof
Application:
60/919,521 →
Chemical removal of oxide layer from chip pads
Application:
60/994,946 →
Wafer prober integrated with full-wafer contacter
Application:
61/069,457 →
Method of testing thinned and singulated die at the wafer level
Application:
61/113,507 →
Method of adding one or more layers of conductive traces and pads to the surface of a fully manufactured wafer including connection to all or a selected sub set of the pads on the die within the wafer
Application:
61/113,544 →
Retractable Protection Mechanism For Electrical Connection Pins
Application:
61/143,355 →
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.