IP Library Granted Patent US 7,489,148
Granted Patent B2
US 7,489,148 · App. 11/881,574 · Granted Feb 10, 2009

Methods for access to a plurality of unsingulated integrated circuits of a wafer using single-sided edge-extended wafer translator

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Quick Facts
Patent No.
US 7,489,148
App. No.
11/881,574
Granted
Feb 10, 2009
Kind
B2
Abstract

An apparatus for providing electrical pathways between one or more unsingulated integrated circuits and one or more test circuits external to the integrated circuits, includes a flexible substrate having a first major surface and a second major surface, a plurality of first contact structures disposed in a central portion of the first surface of the flexible substrate, a plurality of second contact structures disposed in a peripheral annular region of the first surface of the flexible substrate, and a plurality of first electrically conductive pathways, each of the plurality of first electrically conductive pathways coupled to a respective first and second contact structure, wherein the second surface is free from first contact structures, second contact structures, and first electrically conductive pathways.

Claims (14)

1. A method of providing access to a plurality of unsingulated integrated circuits on a wafer, comprising:

providing a first support structure, the first support structure having a first major surface and a second major surface; the first major surface thereof adapted to receive a wafer, and the second major surface thereof adapted to electrically couple to tester pin electronics external to the integrated circuits;

disposing a wafer, the wafer having a plurality of unsingulated integrated circuits thereon, on the first major surface of the first support structure;

disposing a central portion of a removably attachable, single-sided edge-extended wafer translator over the wafer, and a peripheral portion of the removably attachable, single-sided edge-extended wafer translator on the first surface of the first support structure; and

evacuating one or more gases from between the central portion of the removably attachable, single-sided edge-extended wafer translator and the wafer

wherein the step of evacuating results in the wafer and the central portion of the removably attachable single-sided edge-extended wafer translator being removably attached to each other.

2. The method of claim 1 , further comprising evacuating one or more gases from between the peripheral portion of the removably attachable, single-sided edge-extended wafer translator and the first surface of the first support structure.

3. The method of claim 2 , wherein first contact structures disposed in a wafer-side central portion of removably attachable, single-sided edge-extended wafer translator are in electrical contact with corresponding pads on the wafer; and second contact structures disposed in the wafer-side peripheral region of removably attachable, single-sided edge-extended wafer translator are in electrical contact with corresponding contact terminals disposed on the first surface of the first support structure.

4. The method of claim 3 , wherein the first major surface of the first support structure is planar; wherein the wafer has a backside, wherein the backside of the wafer is disposed on the first major surface of the first support structure; and wherein the backside of the wafer and the second contact structures are substantially coplanar with each other.

5. The method of claim 2 , wherein the one or more gases are evacuated through one or more evacuation pathways in the removably attachable, single-sided edge-extended wafer translator.

6. The method of claim 1 , wherein the first support structure is a tester main board.

7. The method of claim 1 , wherein disposing the wafer of the first support structure comprises disposing backside of the wafer on the first support structure.

8. The method of claim 1 , further comprising communicating signals from a plurality of pin electronics through the first support structure to the peripheral portion of the single-sided edge-extended wafer translator.

9. The method of claim 1 , wherein the single-sided edge-extended wafer translator is flexible.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Apr 7, 2021
From: PENINSULA MASTER FUND, LTD.; PENINSULA TECHNOLOGY FUND, LP; QVT FUND LP; QUINTESSENCE FUND LP
To: ADVANCED INQUIRY SYSTEMS, INC.
Reel/Frame 055849/0609 →
CHANGE OF NAME Recorded Mar 13, 2015
From: ADVANCED INQUIRY SYSTEMS, INC.
To: TRANSLARITY, INC.
Reel/Frame 035203/0773 →
SECURITY INTEREST Recorded Sep 21, 2009
From: ADVANCED INQUIRY SYSTEMS, INC.
To: PENINSULA MASTER FUND, LTD.; PENINSULA TECHNOLOGY FUND, LP; QVT FUND LP; QUINTESSENCE FUND LP
Reel/Frame 023282/0070 →
CHANGE OF NAME Recorded Jan 2, 2009
From: OCTAVIAN SCIENTIFIC, INC.
To: ADVANCED INQUIRY SYSTEMS, INC.
Reel/Frame 022060/0135 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2007
From: JOHNSON, MORGAN T.
To: OCTAVIAN SCIENTIFIC, INC.
Reel/Frame 019677/0382 →