Methods for multi-modal wafer testing using edge-extended wafer translator
View Patent ↗Access to integrated circuits of a wafer for concurrently performing two or more types of testing, is provided by bringing a wafer and an edge-extended wafer translator into an attached state. The edge-extended wafer translator having wafer-side contact terminals and inquiry-side contact terminals disposed thereon, a first set of wafer-side contact terminals being electrically coupled to a first set of inquiry-side contact terminals, and a second set of wafer-side contact terminals being electrically coupled to a second set of inquiry-side contact terminals. The edge-extended wafer translator having a central portion generally coextensive with the attached wafer, and an edge-extended portion extending beyond the boundary generally defined by the outer circumferential edge of the wafer. A first set of pads of at least one integrated circuit is electrically coupled to the first set of wafer-side contact terminals, and a second set of pads of the integrated circuit is electrically coupled to the second set of wafer-side contact terminals. The edge-extended wafer translator may be shaped such that its edge-extended portion is not coplanar with the central portion thereof.
1. A method of providing concurrent access to one or more integrated circuits on a wafer, comprising:
providing an edge-extended wafer translator having a central portion and an edge-extended portion, the edge-extended portion vertically offset from the central portion; and
removably attaching a wafer to the central portion of the edge-extended wafer translator, the wafer having integrated circuits thereon;
wherein removably attaching the wafer to the central portion brings a first plurality of wafer-side contact terminals into electrical contact with a first set of pads on the wafer, and brings a second plurality of wafer-side contact terminals into electrical contact with a second set of pads on the wafer; and wherein the first plurality of wafer-side contact terminals are electrically connected to a first plurality of inquiry-side contact terminals disposed on the central portion of the edge-extended wafer translator, and the second plurality of wafer-side contacts are electrically connected to a second plurality of inquiry-side contact terminals disposed on the edge-extended portion of edge-extended wafer translator;
further comprising mounting the edge-extended wafer translator to a mounting fixture;
wherein mounting the edge-extended wafer translator to the mounting fixture comprises disposing the vertically offset edge-extended portion upon the mounting fixture;
further comprising contacting a portion of the first pluralrty of inquiry-side contact terminal with the probes of a probe card.
2. The method of claim 1 , further comprising contacting a portion of the second plurality of inquiry-side contact terminals with DFT/BIST probe pins.
3. The method of claim 1 , further comprising mounting the edge-extended wafer translator to a mounting fixture; wherein the mounting fixture is integral to a wafer prober.
4. A method of providing concurrent access to one or more integrated circuits on a wafer, comprising:
providing an edge-extended wafer translator having a central portion and an edge-extended portion, the edge-extended portion vertically offset from the central portion; and
removably attaching a wafer to the central portion of the edge-extended wafer translator, the wafer having integrated circuits thereon;
wherein removably attaching the wafer to the central portion brings a first plurality of wafer-side contact terminals into electrical contact with a first set of pads on the wafer, and brings a second plurality of wafer-side contact terminals into electrical contact with a second set of pads on the wafer; and wherein the first plurality of wafer-side contact terminals are electrically connected to a first plurality of inquiry-side contact terminals disposed on the central portion of the edge-extended wafer translator, and the second plurality of wafer-side contacts are electrically connected to a second plurality of inquiry-side contact terminals disposed on the edge-extended portion of edge-extended wafer translator, further comprising:
providing electrical connection between at least a first portion of the first plurality of inquiry-side contact terminals and a first tester, the first tester operable to perform a first type of test upon an integrated circuit; and
providing electrical connection between at least a first portion of the second plurality of inquiry-side contact terminals and second tester, the second tester operable to perform a second type of test upon an integrated circuit;
wherein the first portion of the first plurality of inquiry-side contact terminals and the first portion of the second plurality of inquiry-side contact terminals are electrically coupled to corresponding pads of one integrated circuit.
5. The method of claim 4 , wherein the first type of test is a functional test and the second type of test is a BIST test.
6. The method of claim 4 , further comprising mounting the edge-extended wafer translator to a mounting fixture; wherein the mounting fixture is integral to a wafer prober.
7. A method of providing concurrent access to one or more integrated circuits on a wafer, comprising:
providing an edge-extended wafer translator having a central portion and an edge-extended portion, the edge-extended portion vertically offset from the central portion; and
removably attaching a wafer to the central portion of the edge-extended wafer translator, the wafer having integrated circuits thereon;
wherein removably attaching the wafer to the central portion brings a first plurality of wafer-side contact terminals into electrical contact with a first set of pads on the wafer, and brings a second plurality of wafer-side contact terminals into electrical contact with a second set of pads on the wafer; and wherein the first plurality of wafer-side contact terminals are electrically connected to a first plurality of inquiry-side contact terminals disposed on the central portion of the edge-extended wafer translator, and the second plurality of wafer-side contacts are electrically connected to a second plurality of inquiry-side contact terminals disposed on the edge-extended portion of edge-extended wafer translator;
further comprising:
providing electrical connection between at least a first portion of the first plurality of inquiry-side contact terminals and a first tester, the first tester operable to perform a first type of test upon an integrated circuit; and
providing electrical connection between at least a first portion of the second plurality of inquiry-side contact terminals and second tester, the second tester operable to perform a second type of test upon an integrated circuit;
wherein the first portion of the first plurality of inquiry-side contact terminals are electrically coupled to corresponding pads of a first integrated circuit, and the first portion of the second plurality of inquiry-side contact terminals are electrically coupled to corresponding pads of a second integrated circuit.
8. The method of claim 7 , wherein the first type of test is a functional test and the second type of test is a BIST test.
9. The method of claim 7 , further comprising mounting the edge-extended wafer translator to a mounting fixture; wherein the mounting fixture is integral to a wafer prober.