PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPS) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAS, DPGAS, AND THE LIKE)
In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.
1 . A field programmable gate array (FPGA) device, comprising
configurable elements;
a unit for configuring the configurable elements; and
at least two memory units;
wherein:
at least some of the configurable elements are configurable logic elements;
at least some of the configurable elements are configurable ALU elements comprise an ALU unit;
the at least two memories store data processed by at least some of the configurable ALU elements.
2 . The field programmable gate array according to claim 1 , wherein each of the at least some of the configurable elements receives its configuration data during operation.
3 . The field programmable gate array according to claim 1 , wherein each of the at least some of the configurable elements receives its configuration data during operation from other configurable elements.
4 . The field programmable gate array according to any one of claims 1 , 2 , and 3 , wherein at least one of the memory units supports a FIFO mode.
5 . The field programmable gate array according to any one of claims 1 , 2 , and 3 , wherein at least one of the memory units supports simultaneous write and read access.
6 . The field programmable gate array according to any one of claims 1 , 2 , and 3 , wherein at least one of the memory units supports separate write pointers and read pointers.
7 . The field programmable gate array according to claim 6 , wherein at least one of the memory units supports simultaneous write and read access.
8 . The field programmable gate array according to claim 6 , wherein at least one of the memory units is configurable as read memory.
9 . The field programmable gate array according to claim 6 , wherein at least one of the memory units is configurable as write memory.
10 . The field programmable gate array according to claim 6 , wherein at least one of the memory units is alternatively configured as read or write memory.
11 . The field programmable gate array according to any one of claims 1 , 2 , and 3 , wherein at least one of the memory units supports double buffering.
12 . The field programmable gate array according to any one of claims 1 , 2 , and 3 , wherein at least one of the memory units is configurable as read memory.
13 . The field programmable gate array according to any one of claims 1 , 2 , and 3 , wherein at least one of the memory units is configurable as write memory.
14 . The field programmable gate array according to any one of claims 1 , 2 , and 3 , wherein at least one of the memory units is alternatively configured as read or write memory.
15 . A runtime programmable data processing device, comprising:
configurable elements;
a unit for configuring the configurable elements; and
at least two memory units;
wherein:
at least some of the configurable elements are configurable ALU elements comprising an ALU unit;
the at least two memory units store data processed by at least some of the configurable ALU elements; and
at least some of the configurable elements receive configuration data during operation from other configurable elements.
16 . The runtime programmable data processing device according to claim 15 , wherein at least one of the configurable elements is configured as a controller providing configuration data during the operation to at least some others of the configurable elements.
17 . The runtime programmable data processing device according to claim 15 , wherein at least one of the configurable elements is configured as a sequencer providing configuration data during operation to at least some others of the configurable elements.
18 . The runtime programmable data processing device according to claim 15 , wherein a configurable memory integrated in the runtime programmable data processing device is configured to provide configuration data during the operation to at least some others of the configurable elements.
19 . The runtime programmable data processing device according to claim 18 , wherein the configurable memory is addressable.
20 . The runtime programmable data processing device according to claim 19 , wherein the configurable memory is cyclically addressed.
21 . The runtime programmable data processing device according to any one of claims 15 , 16 , 17 , 18 , 19 , and 20 , wherein the runtime programmable processing device is a Field Programmable Gate Array (FPGA).
22 . The runtime programmable data processing device according to claim 15 , wherein at least one of the memory units supports a FIFO mode.
23 . The runtime programmable data processing device according to claim 15 , wherein at least one of the memory units supports separate write pointers and read pointers.
24 . The runtime programmable data processing device according to claim 15 , wherein at least one of the memory units supports simultaneous write and read access.
25 . The runtime programmable data processing device according to claim 15 , wherein at least one of the memory units supports double buffering.
26 . The runtime programmable data processing device according to claim 15 , wherein at least one of the memory units is configurable as read memory.
27 . The runtime programmable data processing device according to claim 15 , wherein at least one of the memory units is configurable as write memory.
28 . The runtime programmable data processing device according to claim 15 , wherein at least one of the memory units is alternatively configured as read or write memory.