Patent Assignment
Reel/Frame 023882/0403
Assignment of Assignor's Interest
Recorded: 2010-02-02
Pages: 39
Assignor
PACT XPP TECHNOLOGIES AG
Executed: 2009-06-26
Assignees
RICHTER, THOMAS, MR.
ALTENHOF 25B, BOCKELWITZ, D-04703, GERMANY
KRASS, MAREN, MS.
KRAHBULSTRASSE 45, ZURICH, CH-8044, SWITZERLAND
Covered Properties
(62)
Unit for Processing Numerical and Logical Operations for Use in Central Processing Units (Cpus), Multiprocessor Systems, Data -Flow Processors (Dsps), Systolic Processors and Field Programmable Gate Arrays (Fpgas)
Patent:
6,425,068 →
Application:
08/946,810 →
Method of the Self-Synchronization of Configurable Elements of a Programmable Unit
Patent:
6,081,903 →
Application:
08/946,812 →
Run-Time Reconfiguration Method for Programmable Units
Patent:
6,021,490 →
Application:
08/946,998 →
Method for the Automatic Address Generation of Modules Within Clusters Comprised of a Plurality of These Modules
Patent:
6,038,650 →
Application:
08/946,999 →
Internal Bus System for Dfps and Units with Two-or Multi-Dimensional Programmable Cell Architectures, for Managing Large Volumes of Data with a High Interconnection Complexity
Patent:
6,405,299 →
Application:
09/145,139 →
Run-Time Reconfiguration Method for Programmable Units
Patent:
7,174,443 →
Application:
09/494,567 →
Method of Repairing Integrated Circuits
Patent:
6,697,979 →
Application:
09/598,926 →
Method for Hierarchical Caching of Configuration Data Having Dataflow Processors and Modules Having Two-or Multidimensional Programmable Cell Structure (Fpgas, Dpgs, Etc.)--
Patent:
6,480,937 →
Application:
09/623,052 →
Method for Deadlock-Free Configuration of Dataflow Processors and Modules with a Two-or Multidimensional Programmable Cell Structure (Fpgas, Dpgas, Etc.)
Patent:
6,571,381 →
Application:
09/623,113 →
Method of Producing a Wetlaid Thermobonded Web-Shaped Fibrous Material and Material Produced by the Method
Method for Debugging Reconfigurable Architectures
Method for Translating Programs for Reconfigurable Architectures
Method for Interleaving a Program Over a Plurality of Cells
Patent:
8,230,411 →
Application:
10/009,649 →
Internal Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures, for Managing Large Volumes of Data with a High Interconnection Complexity
Method of Hierarchical Caching of Configuration Data Having Dataflow Processors and Modules Having Two-or Multidimensional Programmable Cell Structure (Fpgas, Dpgas, Etc.)
Pipeline Configuration Unit Protocols and Communication
L/O and Memory Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures
Method of Self-Synchronization of Configurable Elements of a Programmable Unit
Method of Self-Synchronization of Configurable Elements of a Programmable Module
Methods and Devices for Treating and Processing Data
Method and Device for Treating and Processing Data
Application:
10/469,910 →
Publication:
US 2007/0299993
Methods and Devices for Treating and/or Processing Data
Method for Processing Data
Method for the Translation of Programs for Reconfigurable Architectures
Parallel Task Operation in Processor and Reconfigurable Coprocessor Configured Based on Information in Link List Including Termination Information for Synchronization
Method for Debugging Reconfigurable Architectures
Router
Device Including a Field Having Function Cells and Information Providing Cells Controlled by the Function Cells
Reconfigurable General Purpose Processor Having Time Restricted Configurations
Method of compilation
Application:
10/501,903 →
Publication:
US 2005/0132344
Bus Systems and Reconfiguration Methods
Method and device for data processing
Application:
10/508,559 →
Publication:
US 2006/0075211
Method and Device for Processing Data
Data Processing Method and Device
Reconfigurable Sequencer Structure
Method and device for data processing
Application:
10/551,891 →
Publication:
US 2007/0011433
Data processing device and method
Application:
10/561,135 →
Publication:
US 2007/0083730
Data Processing Device and Method
Method and System for Alternating Between Programs for Execution by Cells of an Integrated Circuit
Method of Hierarchical Caching of Configuration Data Having Dataflow Processors and Modules Having Two- or Multidimensional Programmable Cell Structure (Fpgas, Dpgas, Etc.)
Runtime Configurable Arithmetic and Logic Cell
I/O and Memory Bus System for Dfps and Units with Two-or Multi-Dimensional Programmable Cell Architectures
Pipeline Configuration Protocol and Configuration Unit Communication
Process for Automatic Dynamic Reloading of Data Flow Processors (Dfps) and Units with Two- or Three-Dimensional Programmable Cell Architectures (Fpgas, Dpgas, and the Like
Processor Chip for Reconfigurable Data Processing, for Processing Numeric and Logic Operations and Including Function and Interconnection Control Units.
I/O and Memory Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures
Low Latency Massive Parallel Data Processing Device
Application:
11/883,670 →
Publication:
US 2009/0031104
Method for Debugging Reconfigurable Architectures
I/O and Memory Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures
Reconfigurable Sequencer Structure
Hardware Definition Method Including Determining Whether to Implement a Function as Hardware or Software
Method of Self-Synchronization of Configurable Elements of a Programmable Module
Patent:
44,383 →
Application:
12/109,280 →
Router
Methods and Devices for Treating and Processing Data
Data Processing Device and Method
Method for Debugging Reconfigurable Architectures
Process for Automatic Dynamic Reloading of Data Flow Processors (Dfps) and Units with Two- or Three-Dimensional Programmable Cell Architectures (Fpgas, Dpgas, and the Like)
Application:
12/367,055 →
Publication:
US 2009/0144485
A Circuit Having a Multidimensional Structure of Configurable Cells That Include Multi-Bit-Wide Inputs and Outputs
Logic Cell Array and Bus System
Method and Device for Treating and Processing Data
Application:
12/389,116 →
Publication:
US 2009/0210653
PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPs) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAs, DPGAs AND THE LIKE)
Application:
12/389,155 →
Publication:
US 2009/0153188
Electron Beam Applying Apparatus and Drawing Apparatus
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.