Patent Assignment
Reel/Frame 045532/0745
Assignment of Assignor's Interest
Recorded: 2018-03-16
Pages: 9
Assignor
PACT XPP TECHNOLOGIES AG
Executed: 2018-03-15
Assignee
SCIENTIA SOL MENTIS AG
NEUHOFSTRASSE 1, SCHINDELLEGI, 8834, SWITZERLAND
Covered Properties
(107)
Unit for Processing Numerical and Logical Operations for Use in Central Processing Units (Cpus), Multiprocessor Systems, Data -Flow Processors (Dsps), Systolic Processors and Field Programmable Gate Arrays (Fpgas)
Patent:
6,425,068 →
Application:
08/946,810 →
Method of the Self-Synchronization of Configurable Elements of a Programmable Unit
Patent:
6,081,903 →
Application:
08/946,812 →
Run-Time Reconfiguration Method for Programmable Units
Patent:
6,021,490 →
Application:
08/946,998 →
Method for the Automatic Address Generation of Modules Within Clusters Comprised of a Plurality of These Modules
Patent:
6,038,650 →
Application:
08/946,999 →
Process for Automatic Dynamic Reloading of Data-Flow Processors (Dfps) and Units with Two-or Three-Dimensional Programmable Cell Architectures (Fpgas, Dpgas and the Like)
Patent:
6,088,795 →
Application:
08/947,002 →
I/O and Memory Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures
Patent:
6,119,181 →
Application:
08/947,254 →
Internal Bus System for Dfps and Units with Two-or Multi-Dimensional Programmable Cell Architectures, for Managing Large Volumes of Data with a High Interconnection Complexity
Patent:
6,405,299 →
Application:
09/145,139 →
Runtime Configurable Arithmetic and Logic Cell
Patent:
6,728,871 →
Application:
09/329,132 →
I/O and Memory Bus System for Dfps and Units with Two or Multi-Dimensional Programmable Cell Architectures
Patent:
6,338,106 →
Application:
09/335,974 →
Method of Self-Synchronization of Configurable Elements of a Programmable Module
Patent:
6,542,998 →
Application:
09/369,653 →
Run-Time Reconfiguration Method for Programmable Units
Patent:
7,174,443 →
Application:
09/494,567 →
Method of Self-Synchronization of Configurable Elements of a Programmable Unit
Patent:
6,526,520 →
Application:
09/537,932 →
Process for Automatic Dynamic Reloading of Data Flow Processors (Dfps) and Units with Two-or Three-Dimensional Programmable Cell Architectures (Fpgas,Dpgas, and the Like)
Patent:
6,477,643 →
Application:
09/613,217 →
Method for Hierarchical Caching of Configuration Data Having Dataflow Processors and Modules Having Two-or Multidimensional Programmable Cell Structure (Fpgas, Dpgs, Etc.)--
Patent:
6,480,937 →
Application:
09/623,052 →
Method for Deadlock-Free Configuration of Dataflow Processors and Modules with a Two-or Multidimensional Programmable Cell Structure (Fpgas, Dpgas, Etc.)
Patent:
6,571,381 →
Application:
09/623,113 →
I/O and Memory Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures
Method for Debugging Reconfigurable Architectures
Method for Translating Programs for Reconfigurable Architectures
Method for Interleaving a Program Over a Plurality of Cells
Patent:
8,230,411 →
Application:
10/009,649 →
Reconfigurable Multidimensional Array Processor Allowing Runtime Reconfiguration of Selected Individual Array Cells
Method of Hierarchical Caching of Configuration Data Having Dataflow Processors and Modules Having Two-or Multidimensional Programmable Cell Structure (Fpgas, Dpgas, Etc.)
Process for Automatic Dynamic Reloading of Data Flow Processors (Dfps) and Units with Two- or Three-Dimensional Programmable Cell Architectures (Fpgas, Dpgas, and the Like)
Pipeline Configuration Unit Protocols and Communication
L/O and Memory Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures
Method of Self-Synchronization of Configurable Elements of a Programmable Unit
Method of Self-Synchronization of Configurable Elements of a Programmable Module
Logic Cell Array and Bus System
Methods and Devices for Treating and Processing Data
Methods and Devices for Treating and/or Processing Data
Method for Processing Data
Method for the Translation of Programs for Reconfigurable Architectures
Method for Debugging Reconfigurable Architectures
Router
Device Including a Field Having Function Cells and Information Providing Cells Controlled by the Function Cells
Method and Device for Processing Data
Data Processing Method and Device
Reconfigurable Sequencer Structure
Data Processing Device and Method
Method and System for Alternating Between Programs for Execution by Cells of an Integrated Circuit
Method of Hierarchical Caching of Configuration Data Having Dataflow Processors and Modules Having Two- or Multidimensional Programmable Cell Structure (Fpgas, Dpgas, Etc.)
Runtime Configurable Arithmetic and Logic Cell
I/O and Memory Bus System for Dfps and Units with Two-or Multi-Dimensional Programmable Cell Architectures
Pipeline Configuration Protocol and Configuration Unit Communication
Process for Automatic Dynamic Reloading of Data Flow Processors (Dfps) and Units with Two- or Three-Dimensional Programmable Cell Architectures (Fpgas, Dpgas, and the Like
Processor Chip for Reconfigurable Data Processing, for Processing Numeric and Logic Operations and Including Function and Interconnection Control Units.
I/O and Memory Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures
Method for Debugging Reconfigurable Architectures
I/O and Memory Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures
Reconfigurable Sequencer Structure
Hardware Definition Method Including Determining Whether to Implement a Function as Hardware or Software
Method of Self-Synchronization of Configurable Elements of a Programmable Module
Patent:
44,383 →
Application:
12/109,280 →
Router
Methods and Devices for Treating and Processing Data
Data Processing Device and Method
Method for Debugging Reconfigurable Architectures
A Circuit Having a Multidimensional Structure of Configurable Cells That Include Multi-Bit-Wide Inputs and Outputs
Logic Cell Array and Bus System
Data Processing Device and Method
Data Processor Having Disabled Cores
Reconfigurable Sequencer Structure
Data Processing Method and Device
Methods and Devices for Treating and Processing Data
Reconfigurable Elements
Method and Device for Processing Data
I/O and Memory Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures
Configurable Logic Integrated Circuit Having a Multidimensional Structure of Configurable Elements
Multi-Core Processing System
A Processor Chip Including a Plurality of Cache Elements Connected to a Plurality of Processor Cores
I/O and Memory Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures
Method of Self-Synchronization of Configurable Elements of a Programmable Module
Patent:
44,365 →
Application:
12/909,061 →
Method of Self-Synchronization of Configurable Elements of a Programmable Module
Patent:
45,223 →
Application:
12/909,150 →
Method of Self-Synchronization of Configurable Elements of a Programmable Module
Patent:
45,109 →
Application:
12/909,203 →
Processor Arrangement on a Chip Including Data Processing, Memory, and Interface Elements
Reconfigurable Elements
Reconfigurable Sequencer Structure
Method for the Translation of Programs for Reconfigurable Architectures
Method for Debugging Reconfigurable Architectures
Logic Cell Array and Bus System
Pipeline Configuration Protocol and Configuration Unit Communication
Reconfigurable Sequencer Structure
Methods and Devices for Treating and Processing Data
Logical Cell Array and Bus System
Multiprocessor Having Runtime Adjustable Clock and Clock Dependent Power Supply
Method for processing data
Chip Including Memory Element Storing Higher Level Memory Data on a Page by Page Basis
Reconfigurable Elements
Configurable Logic Integrated Circuit Having a Multidimensional Structure of Configurable Elements
Multi-core processor having disabled cores
Multi-processor bus and cache interconnection system
Multi-processor with selectively interconnected memory units
Parallel Processing Array of Arithmetic Unit having a Barrier Instruction
Application:
14/465,157 →
Publication:
US 2015/0033000
Method of Processing Data with an Array of Data Processors According to Application ID
Multiprocessor Having Segmented Cache Memory
Application:
14/540,782 →
Publication:
US 2015/0074352
Multiprocessor Having Associated RAM Units
Data Processing System Having Integrated Pipelined Array Data Processor
Data Processor Chip with Flexible Bus System
Methods and Systems for Transferring Data between a Processing Device and External Devices
Stacked-Die Multi-Processor
Integrated data processing core and array data processor and method for processing algorithms
Processor Having a Programmable Function Unit
Array Processor Having a Segmented Bus System
Multi-processor with selectively interconnected memory units
Method of Transferring Data between External Devices and an Array Processor
Methods and devices for treating and processing data
Array Processor Having a Segmented Bus System
Application:
15/488,384 →
Publication:
US 2018/0300278
Method for Providing Subapplications to an Array of Alus
Multi-Processor with Selectively Interconnected Memory Units
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.