Reconfigurable elements
View Patent ↗A cell element field for data processing having function cells for execution of algebraic and/or logic functions and memory cells for receiving, storing and/or outputting information is described. A control connection may lead from the function cells to the memory cells.
1. A Field Programmable Gate Array (FPGA) integrated device comprising:
at least two dies that are stacked;
a configurable interconnect structure;
an arrangement of configurable cells interconnected by the configurable interconnect structure; wherein:
at least some of the configurable cells include Arithmetic Logic Units (ALUs);
the configurable interconnect structure includes switching elements;
the configurable cells are implemented on at least a first one of the at least two dies; and
at least parts of an interconnect structure are implemented on at least a second one of the at least two dies.
2. The FPGA integrated device according to claim 1 , further comprising at least one dedicated interface unit that interfaces between the programmable data processing units and a device external to the FPGA integrated device.
3. The FPGA integrated device according to claim 2 , further comprising at least one dedicated Peripheral Component Interconnect (PCI) unit.
4. The FPGA integrated device according to claim 2 , further comprising at least one dedicated Ethernet unit.
5. The FPGA integrated device according to claim 1 , wherein at least some of the ALUs are capable of splitting operands into a respective set of data, data of which is processable independently of each other and splitting a result into a respective set of data, data of which is processable independently of each other.
6. The FPGA integrated device according to claim 5 , wherein the interconnect structure is capable of transmitting each data part of each of the sets of data separately.
7. The FPGA integrated device according to claim 1 , wherein at least some of the ALUs are capable of single instruction multiple data (SIMD) processing.
8. The FPGA integrated device according to claim 7 , wherein the interconnect structure is capable of transmitting each data part of each of the sets of data separately.
9. The FPGA integrated device according to claim 1 , wherein at least some switches of the interconnect structure are implemented on the second die.
10. The FPGA integrated device according to claim 1 , wherein at least some of the dies are interconnected by vias.
11. The FPGA integrated device according to claim 10 , wherein the vias extend through a silicon layer.
12. The FPGA integrated device according to claim 1 , wherein the at least parts of the interconnect structure implemented on the at least a second one of the at least two dies includes the configurable interconnect structure.
13. The FPGA Integrated device according to claim 1 , wherein the at least parts of the interconnect structure on the at least a second one of the at least two dies comprises switching elements.
14. The FPGA Integrated device according to claim 1 , wherein all of the at least two dies in the stack are identical.
15. The FPGA Integrated device according to claim 1 , wherein at least some of the dies in the stack are different from other dies that are stacked.
16. The FPGA Integrated device according to claim 1 , wherein at least one die in the stack comprises an ALU and at least one die in the stack comprises an input/output component.
17. The FPGA Integrated device according to any one of claims 1 , 14 , 15 and 16 , wherein at least one smaller die is mounted on top of the first die.
18. The FPGA Integrated device according to claim 17 , wherein a plurality of dies is mounted on top of the first die.
19. The FPGA Integrated device according to claim 1 , wherein a plurality of dies is mounted on top of the first die.
20. The FPGA Integrated device according to claim 19 , wherein at least some vertical connections of the FPGA are made through vias extending through a silicon layer.
21. The FPGA Integrated device according to any one of claims 1 and 10 , wherein at least some of the dies are interconnected by bumps.
22. The FPGA Integrated device according to claim 1 , wherein external interfaces are implemented on at least a third die.
23. The FPGA Integrated device according to any one of claims 1 and 22 , wherein at least some vertical connections of the FPGA are made through vias extending through a silicon layer.
24. The FPGA Integrated device according to claim 23 , wherein at least some of the dies are interconnected by bumps.
25. The FPGA Integrated device according to claim 1 , wherein the first die comprises wiring.
26. The FPGA Integrated device according to claim 1 , wherein the first die comprises solely wiring.
27. The FPGA Integrated device according to claim 1 , wherein the first die comprises switching elements.
28. The FPGA Integrated device according to claim 1 , wherein the first die comprises switching elements and wiring.
29. A system comprising:
at least one processor; and
at least one data processing device communicatively coupled to the processor;
wherein:
the data processing device includes an arrangement of configurable cells interconnected by a configurable interconnect structure;
at least some of the configurable cells include Arithmetic Logic Units (ALUs);
the configurable interconnect structure includes switching elements;
the configurable cells are implemented on at least a first one of at least two dies that are stacked; and
at least parts of an interconnect structure are implemented on at least a second one of the at least two dies.
30. The system according to claim 29 , wherein the at least one processor and the at least one data processing device are connected via an interface implemented on a die of the data processing device.
31. The system according to claim 29 , wherein the at least one data processing device is a Field Programmable Gate Array (FPGA) device.
32. The system according to claim 29 , wherein the at least one data processing device comprises Field Programmable Gate Array (FPGA) cells.
33. The system according to claim 29 , further comprising at least one interface unit dedicated to the data processing device and that interfaces between the data processing device and a device external to a chip on which the data processing device is positioned.
34. The system according to claim 33 , further comprising at least one Peripheral Component Interconnect (PCI) unit dedicated to the data processing device.
35. The system according to claim 31 , further comprising at least one Ethernet unit dedicated to the data processing device.
36. The system according to claim 29 , wherein at least some of the ALUs are capable of splitting operands into a respective set of data, data of which is processable independently of each other and splitting a result into a respective set of data, data of which is processable independently of each other.
37. The system according to claim 36 , wherein the interconnect structure is capable of transmitting each data part of each of the sets of data separately.
38. The system according to claim 29 , wherein at least some of the ALUs are capable of single instruction multiple data (SIMD) processing.
39. The system according to claim 38 , wherein the interconnect structure is capable of transmitting each data part of each of the sets of data separately.
40. The system according to claim 29 , wherein at least some switches of the interconnect structure are implemented on the second die.
41. The system according to claim 29 , wherein at least some of the dies are interconnected by vias.
42. The system according to claim 29 , wherein the at least parts of the interconnect structure implemented on the at least a second one of the at least two dies includes the configurable interconnect structure.
43. The system according to claim 29 , wherein the at least parts of the interconnect structure on the at least a second one of the at least two dies comprises switching elements.
44. The system according to claim 29 , wherein all of the at least two dies in the stack are identical.
45. The system according to claim 29 , wherein at least some of the dies in the stack are different from other dies that are stacked.
46. The system according to claim 29 , wherein at least one die in the stack comprises an ALU and at least one die in the stack comprises an input/output component.
47. The system according to any one of claims 29 , 44 , 45 and 46 , wherein at least one smaller die is mounted on top of the first die.
48. The system according to claim 47 , wherein a plurality of dies is mounted on top of the first die.
49. The system according to claim 29 , wherein a plurality of dies is mounted on top of the first die.
50. The system according to claim 49 , wherein at least some vertical connections of the FPGA are made through vias extending through a silicon layer.
51. The system according to any one of claims 29 and 41 , wherein at least some of the dies are interconnected by bumps.
52. The system according to claim 29 , wherein external interfaces are implemented on at least a third die.
53. The system according to any one of claims 29 and 52 , wherein at least some vertical connections of the FPGA are made through vias extending through a silicon layer.
54. The system according to claim 53 , wherein at least some of the dies are interconnected by bumps.
55. The system according to claim 29 , wherein the first die comprises wiring.
56. The system according to claim 29 , wherein the first die comprises solely wiring.
57. The system according to claim 29 , wherein the first die comprises switching elements.
58. The system according to claim 29 , wherein the first die comprises switching elements and wiring.