Patent Assignment
Reel/Frame 032225/0089
Assignment of Assignor's Interest
Recorded: 2014-02-08
Pages: 51
Assignee
PACT XPP TECHNOLOGIES AG
WALTER-GROPIUS-STR. 15 80807, MUNICH, GERMANY
Covered Properties
(116)
Dynamically Reconfigurable Data Processing System
Patent:
5,943,242 →
Application:
08/544,435 →
Unit for Processing Numerical and Logical Operations for Use in Central Processing Units (Cpus), Multiprocessor Systems, Data -Flow Processors (Dsps), Systolic Processors and Field Programmable Gate Arrays (Fpgas)
Patent:
6,425,068 →
Application:
08/946,810 →
Method of the Self-Synchronization of Configurable Elements of a Programmable Unit
Patent:
6,081,903 →
Application:
08/946,812 →
Run-Time Reconfiguration Method for Programmable Units
Patent:
6,021,490 →
Application:
08/946,998 →
Method for the Automatic Address Generation of Modules Within Clusters Comprised of a Plurality of These Modules
Patent:
6,038,650 →
Application:
08/946,999 →
Process for Automatic Dynamic Reloading of Data-Flow Processors (Dfps) and Units with Two-or Three-Dimensional Programmable Cell Architectures (Fpgas, Dpgas and the Like)
Patent:
6,088,795 →
Application:
08/947,002 →
I/O and Memory Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures
Patent:
6,119,181 →
Application:
08/947,254 →
Internal Bus System for Dfps and Units with Two-or Multi-Dimensional Programmable Cell Architectures, for Managing Large Volumes of Data with a High Interconnection Complexity
Patent:
6,405,299 →
Application:
09/145,139 →
Data Processing System
Patent:
6,859,869 →
Application:
09/290,342 →
Runtime Configurable Arithmetic and Logic Cell
Patent:
6,728,871 →
Application:
09/329,132 →
I/O and Memory Bus System for Dfps and Units with Two or Multi-Dimensional Programmable Cell Architectures
Patent:
6,338,106 →
Application:
09/335,974 →
Method of Self-Synchronization of Configurable Elements of a Programmable Module
Patent:
6,542,998 →
Application:
09/369,653 →
Run-Time Reconfiguration Method for Programmable Units
Patent:
7,174,443 →
Application:
09/494,567 →
Method of Self-Synchronization of Configurable Elements of a Programmable Unit
Patent:
6,526,520 →
Application:
09/537,932 →
Method of Repairing Integrated Circuits
Patent:
6,697,979 →
Application:
09/598,926 →
Process for Automatic Dynamic Reloading of Data Flow Processors (Dfps) and Units with Two-or Three-Dimensional Programmable Cell Architectures (Fpgas,Dpgas, and the Like)
Patent:
6,477,643 →
Application:
09/613,217 →
Method for Hierarchical Caching of Configuration Data Having Dataflow Processors and Modules Having Two-or Multidimensional Programmable Cell Structure (Fpgas, Dpgs, Etc.)--
Patent:
6,480,937 →
Application:
09/623,052 →
Method for Deadlock-Free Configuration of Dataflow Processors and Modules with a Two-or Multidimensional Programmable Cell Structure (Fpgas, Dpgas, Etc.)
Patent:
6,571,381 →
Application:
09/623,113 →
I/O and Memory Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures
Method for Debugging Reconfigurable Architectures
Method for Translating Programs for Reconfigurable Architectures
Method for Interleaving a Program Over a Plurality of Cells
Patent:
8,230,411 →
Application:
10/009,649 →
Internal Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures, for Managing Large Volumes of Data with a High Interconnection Complexity
Reconfigurable Multidimensional Array Processor Allowing Runtime Reconfiguration of Selected Individual Array Cells
Method of Hierarchical Caching of Configuration Data Having Dataflow Processors and Modules Having Two-or Multidimensional Programmable Cell Structure (Fpgas, Dpgas, Etc.)
Process for Automatic Dynamic Reloading of Data Flow Processors (Dfps) and Units with Two- or Three-Dimensional Programmable Cell Architectures (Fpgas, Dpgas, and the Like)
Pipeline Configuration Unit Protocols and Communication
L/O and Memory Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures
Method of Self-Synchronization of Configurable Elements of a Programmable Unit
Method of Self-Synchronization of Configurable Elements of a Programmable Module
Logic Cell Array and Bus System
Methods and Devices for Treating and Processing Data
Method and Device for Treating and Processing Data
Application:
10/469,910 →
Publication:
US 2007/0299993
Methods and Devices for Treating and/or Processing Data
Method for Processing Data
Method for the Translation of Programs for Reconfigurable Architectures
Parallel Task Operation in Processor and Reconfigurable Coprocessor Configured Based on Information in Link List Including Termination Information for Synchronization
Method for Debugging Reconfigurable Architectures
Router
Device Including a Field Having Function Cells and Information Providing Cells Controlled by the Function Cells
Reconfigurable General Purpose Processor Having Time Restricted Configurations
Method of compilation
Application:
10/501,903 →
Publication:
US 2005/0132344
Bus Systems and Reconfiguration Methods
Method and device for data processing
Application:
10/508,559 →
Publication:
US 2006/0075211
Method and Device for Processing Data
Data Processing Method and Device
Reconfigurable Sequencer Structure
Method and device for data processing
Application:
10/551,891 →
Publication:
US 2007/0011433
Data processing device and method
Application:
10/561,135 →
Publication:
US 2007/0083730
Data Processing Device and Method
Method and System for Alternating Between Programs for Execution by Cells of an Integrated Circuit
Method of Hierarchical Caching of Configuration Data Having Dataflow Processors and Modules Having Two- or Multidimensional Programmable Cell Structure (Fpgas, Dpgas, Etc.)
Runtime Configurable Arithmetic and Logic Cell
I/O and Memory Bus System for Dfps and Units with Two-or Multi-Dimensional Programmable Cell Architectures
Pipeline Configuration Protocol and Configuration Unit Communication
Process for Automatic Dynamic Reloading of Data Flow Processors (Dfps) and Units with Two- or Three-Dimensional Programmable Cell Architectures (Fpgas, Dpgas, and the Like
Processor Chip for Reconfigurable Data Processing, for Processing Numeric and Logic Operations and Including Function and Interconnection Control Units.
I/O and Memory Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures
Low Latency Massive Parallel Data Processing Device
Application:
11/883,670 →
Publication:
US 2009/0031104
Method for Debugging Reconfigurable Architectures
I/O and Memory Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures
Reconfigurable Sequencer Structure
Hardware Definition Method Including Determining Whether to Implement a Function as Hardware or Software
Method of Self-Synchronization of Configurable Elements of a Programmable Module
Patent:
44,383 →
Application:
12/109,280 →
Router
Methods and Devices for Treating and Processing Data
Data Processing Device and Method
Method for Debugging Reconfigurable Architectures
A Circuit Having a Multidimensional Structure of Configurable Cells That Include Multi-Bit-Wide Inputs and Outputs
Logic Cell Array and Bus System
Method and Device for Treating and Processing Data
Application:
12/389,116 →
Publication:
US 2009/0210653
Data Processing Device and Method
Data Processor Having Disabled Cores
Methods and Devices for Treating and/or Processing Data
Application:
12/496,012 →
Publication:
US 2009/0300262
Reconfigurable Sequencer Structure
Data Processing Method and Device
Methods and Devices for Treating and Processing Data
Reconfigurable Elements
Method for Increasing Configuration Runtime of Time-Sliced Configurations
Application:
12/571,195 →
Publication:
US 2010/0122064
Method and Device for Processing Data
I/O and Memory Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures
Method for Processing Data
Application:
12/640,201 →
Publication:
US 2010/0095094
Configurable Logic Integrated Circuit Having a Multidimensional Structure of Configurable Elements
Processor device having a sequential data processing unit and an arrangement of data processing elements
Application:
12/729,090 →
Publication:
US 2010/0174868
Method and Device for Thread Scheduling Within a Processor Having Multiple Heterogeneous Cores
Application:
12/729,932 →
Publication:
US 2011/0161977
Reconfigurable Floating-Point and Bit-Level Data Processing Unit
Application:
12/743,356 →
Publication:
US 2010/0281235
Method for Facilitating Compilation of High-Level Code for Varying Architectures
Application:
12/745,335 →
Publication:
US 2011/0173596
Using Function Calls as Compiler Directives
Application:
12/746,570 →
Publication:
US 2011/0119657
Multi-Core Processing System
A Processor Chip Including a Plurality of Cache Elements Connected to a Plurality of Processor Cores
Configurable Logic Integrated Circuit Having a Multidimensional Structure of Configurable Elements
Application:
12/840,559 →
Publication:
US 2011/0012640
I/O and Memory Bus System for Dfps and Units with Two- or Multi-Dimensional Programmable Cell Architectures
Method of Self-Synchronization of Configurable Elements of a Programmable Module
Patent:
44,365 →
Application:
12/909,061 →
Method of Self-Synchronization of Configurable Elements of a Programmable Module
Patent:
45,223 →
Application:
12/909,150 →
Method of Self-Synchronization of Configurable Elements of a Programmable Module
Patent:
45,109 →
Application:
12/909,203 →
Processor Arrangement on a Chip Including Data Processing, Memory, and Interface Elements
Method and Device for Coupling a Data Processing Unit and a Data Processing Array
Application:
12/947,167 →
Publication:
US 2011/0238948
Reconfigurable Elements
Low Latency Massive Parallel Data Processing Device
Application:
13/026,475 →
Publication:
US 2012/0017066
Reconfigurable Sequencer Structure
Methods and Devices for Treating and/or Processing Data
Application:
13/043,102 →
Publication:
US 2011/0173389
Method for the Translation of Programs for Reconfigurable Architectures
Method for Debugging Reconfigurable Architectures
Logic Cell Array and Bus System
Bus Systems and Methods for Controlling Data Flow in a Field of Processing Elements
Application:
13/324,048 →
Publication:
US 2012/0151113
Pipeline Configuration Protocol and Configuration Unit Communication
Hardware Definition Method Including Determining Whether to Implement a Function as Hardware or Software
Application:
13/491,935 →
Publication:
US 2012/0278772
Reconfigurable Sequencer Structure
Methods and Devices for Treating and Processing Data
Method for Debugging Reconfigurable Architectures
Application:
13/796,215 →
Publication:
US 2013/0339797
Pipeline Configuration Protocol and Configuration Unit Communication
Application:
13/872,779 →
Publication:
US 2014/0325175
Reconfigurable Elements
Application:
14/149,371 →
I/O and Memory Bus System For DFPS and Units With Two- Or Multi-Dimensional Programmable Cell Architectures
Application:
90/010,450 →
I/O and Memory Bus System for Dfps and Units with Two or Multi-Dimensional Programmable Cell Architectures
Application:
90/010,979 →
I/O and Memory Bus System for DFPS and Units with Two or Multi-Dimensional Programmable Cell Architectures
Application:
90/011,087 →
I/O And Memory Bus System For DFPS And Units With Two Or Multi Dimensional Programmable Cell Architectures
Application:
90/011,798 →
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.