Processor device having a sequential data processing unit and an arrangement of data processing elements

1 - 20 . (canceled)

21 . A processor device comprising:

a sequential data processing unit;

a plurality of data storage elements;

an array of data processing elements connected to the plurality of data storage elements; and

a data cache shared by the sequential data processing unit and the array of data processing elements;

wherein:

the data cache is divided into memory segments;

each of the plurality of data storage elements corresponds to a respective one of the memory segment; and

the processor device is adapted for at least some of the plurality of data storage elements to access their respective memory segment simultaneously, each independently of the others of the plurality of data storage elements.

22 . The processor device of claim 21 , wherein the sequential data processing unit is a central processing unit (CPU).

23 . The processor device of claim 21 , wherein the sequential data processing unit is adapted for accessing the data cache simultaneously and independently from the array of data processing elements.

24 . The processor device of claim 21 , wherein the processor device is adapted for the sequential processing unit to be blocked from accessing some regions of the data cache.

25 . The processor device of claim 21 , wherein the array of data processing elements is part of a runtime reconfigurable processor.

26 . A processor device comprising:

a sequential data processing unit;

an arrangement of data processing elements having vector registers; and

a data cache shared by the sequential data processing unit and the arrangement of data processing elements;

wherein:

the vector registers are directly connected to the data cache; and

the data cache is simultaneously and independently accessible by the sequential data processing unit and the arrangement of data processing elements.

27 . The processor device of claim 26 , wherein the sequential data processing unit is a central processing unit (CPU).

28 . The processor device of claim 26 , wherein the processor device is adapted for the sequential processing unit to be blocked from accessing some regions of the data cache.

29 . The processor device of claim 26 , wherein the vector registers are implemented as a cache segment.

30 . The processor device of claim 26 , further comprising:

an arrangement for bypassing the cache for direct data transfers between the vector registers and memory.

31 . A processor device comprising:

a sequential data processing unit having a register set; and

an arrangement of data processing elements;

an unit adapted for:

in a data transfer defined by an opcode, transferring operand and result data between the register file and the arrangement of data processing elements; and

sorting at least one of the operand and result data so that there is no interference due to different runtimes.

32 . The processor device of claim 31 , wherein the sequential data processing unit is a central processing unit (CPU).

33 . The processor device of claim 31 , wherein the arrangement of data processing elements is part of a runtime reconfigurable processor.

34 . The processor device of claim 31 , wherein the arrangement of data processing elements has vector registers.

35 . A processor device having:

a sequential data processing unit having a register set; and

an arrangement of data processing elements;

a register allocation unit for managing destination registers for data processing results, using opcodes that identify the destination registers.

36 . The processor device of claim 35 , wherein the sequential data processing unit is a central processing unit (CPU).

37 . The processor device of claim 35 , wherein the arrangement of data processing elements is part of a runtime reconfigurable processor.

38 . The processor device of claim 35 , wherein the arrangement of data processing elements has vector registers.