Method for translating programs for reconfigurable architectures
View Patent ↗A method for translating high-level languages to reconfigurable architectures is disclosed. The method includes building a finite automaton for calculation. The method further includes forming a combinational network of a plurality of individual functions in accordance with the structure of the finite automaton. The method further includes allocating a plurality of memories to the network for storing a plurality of operands and a plurality of results.
1. A method for translating a high-level language program into configurations for a reconfigurable architecture, comprising:
building a finite automaton forming a complex combinational network for control flow and data handling using a plurality of individual operations in accordance with the complex combinational structure of the finite automaton;
splitting the finite automaton into configurations, each including at least a part of the control flow handling and at least a part of the data handling, to be successively executed by the reconfigurable architecture, the splitting being performed in a manner that maximizes a number of data packets that are calculable without a reconfiguration; and
allocating a plurality of memories to the network for storing at least one of data and states between at least one pair of successively executed configurations, the at least one of data and states being stored by execution of a first one of the pair and being retrieved from the plurality of memories via execution of a second one of the pair, the second configuration being executed after the first configuration.
2. The method according to claim 1 , further comprising:
for the finite automaton, defining a plurality of rows that are each executable within one clock unit of the architecture;
for each of the plurality of rows, calculating a value based on a number of data words that are processable within the row and a number of arithmetic logic units that are required; and
if the value of more than one of the plurality of rows indicates that the number of data words that are processable within a corresponding row is less than the number of arithmetic logic units that are required for the corresponding row, combining the more than one of the plurality of rows to form a sequence to be configured in the reconfigurable architecture for sequential processing.
3. The method of claim 2 , further comprising:
for each of a plurality of defined sequences, determining a number representing cycles used for processing a function assigned to the sequence; and
in accordance with the determinations, grouping the plurality of defined sequences for configuration onto the reconfigurable architecture.