Data processing method and device
View Patent ↗In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.
1. A processor chip comprising:
a plurality of processor cores, including at least one processor having a plurality of ALUs;
a plurality of local memories comprising copies of main memory areas;
a cache controller controlling at least one of the local memories; wherein:
the processor chip has multi-thread capabilities; and
the cache controller is adapted to receive prefetch requests during execution of a first thread and to prefetch data during the execution of a second thread;
wherein the prefetch commands are software instructions generated by a compiler, and
at least some of the prefetch requests are burst requests to the cache controller; and the burst request comprising a vector stride request.
2. The processor chip of claim 1 wherein a vector stride comprises a displacement of data between two memory elements.
3. The processor chip of claim 2 wherein the displacement of data between two memory elements is greater than the size of a cache line.
4. A method for operating a processor chip that comprises a plurality of processor cores including at least one processor having a plurality of ALUs and having multi-thread capabilities, and that further comprises a plurality of local memories comprising copies of main memory areas, at least some of the local memories operating as first level cache, the method comprising:
prefetching data from the main memory areas into the local memories; the prefetching being initiated by a prefetch command during execution of a first thread; and
prefetching data during the execution of a second thread;
the prefetch command is a software instruction generated by a compiler;
wherein the prefetching step comprises prefetching a vector stride.
5. The method according to claim 4 , wherein at least some parts of the first level cache are shared between the processor cores.
6. The method of claim 4 wherein a vector stride comprises a displacement of data between two memory elements.
7. The method of claim 6 wherein the displacement of data between two memory elements is greater than the size of a cache line.