Data processing device and method
View Patent ↗A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed.
1. A processing device comprising:
a configurable global interconnect structure including a plurality of multi-bit wide interconnects;
a plurality of configurable coarse grained elements; and
at least one dedicated multi-bit wide interconnect that is separate from the configurable global interconnect structure, each of the at least one dedicated multi-bit wide interconnect dedicated for connecting a respective single pair of the plurality of coarse grained elements;
wherein:
each of the coarse grained elements is connected to the global interconnect structure;
the plurality of coarse grained elements are arranged in rows, the rows being interconnected via the global interconnect structure; and
each of at least one of the plurality of coarse grained elements:
(a) includes:
at least one operand data input that is directly and vertically connected via a first one of the at least one dedicated multi-bit wide interconnect to a result data output of a respective first other one of the plurality of coarse grained elements; and
at least one result data output that is directly and vertically connected via a second one of the at least one dedicated multi-bit wide interconnect to an operand data input of a respective second other one of the plurality of coarse grained elements; and
(b) is on a different row than the first and second other ones of the plurality of coarse grained elements; and
(c) is adapted to transfer data from its respective at least one operand data input through units for processing multi-bit arithmetic functions, at least one multiplexer downstream of the units for processing multi-bit arithmetic functions, and at least one register downstream of the at least one multiplexer, to its respective at least one result data output.
2. The processing device according to claim 1 , wherein at least two input/output connects to the global interconnect structure are provided in one row and wherein at least one of (a) a switch in the global interconnect structure and (b) one of a gate, buffer, and multiplexer is provided between the at least two input/output connects.
3. The processing device according to claim 1 , wherein the each of the at least one of the plurality of coarse grained elements, its respective first other one of the plurality of coarse grained elements, and its respective second other one of the plurality of coarse grained elements are arranged in three successive rows.