METHODS AND DEVICES FOR TREATING AND/OR PROCESSING DATA
At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data processing and in particular decoupling of the reconfiguration cycles from the external data streams (to/from peripherals, memories, etc.).
1 - 9 . (canceled)
10 . A processor arrangement on a chip comprising:
at least one data processing element;
at least one local memory element directly connected to at least one of the at least one data processing element;
a Memory Management Unit (MMU); and
an interface unit between the at least one local memory element and a higher level memory;
wherein the local memory element is adapted to buffer complete data pages of the higher level memory.
11 . The processor arrangement according to claim 10 , wherein the at least one local memory has an associated address translation table.
12 . The processor arrangement according to claim 11 , wherein the address translation table is a Translation Lookaside Buffer (TLB).
13 . The processor arrangement according to claim 10 , wherein the higher memory is external to the chip.
14 . The processor arrangement according to claim 10 , further comprising:
an arrangement to move a data page from the higher level memory to the at least one local memory element if the data page is accessed.
15 . The processor arrangement according to claim 10 , further comprising:
an arrangement to move data pages from the higher memory to the at least one local memory element if a page fault occurs.
16 . The processor arrangement according to claim 10 , further comprising:
an arrangement to translate a virtual address into a physical address of the at least one local memory element.
17 . The processor arrangement according to claim 10 , further comprising:
an arrangement to unload pages from the at least one local memory element to the higher memory.
18 . The processor arrangement according to claim 10 , further comprising:
an arrangement to unload pages from the at least one local memory element to the higher memory if the at least one local memory has no space to store additional new pages.
19 . The processor arrangement according to claim 10 , further comprising:
an address translation table for translating virtual addresses into physical addresses of the at least one local memory.
20 . The processor arrangement according to claim 10 , further comprising:
an address translation table associated with the local memory issuing a Page Fault in case a page is not stored in the local memory.
21 . The processor arrangement according to any one of claims 19 and 20 , wherein the address translation table is a Translation Lookaside Buffer (TLB).
22 . A processor arrangement on a chip comprising:
a plurality of data processing elements;
a plurality of local memory elements, the plurality of local memory elements being connected to the plurality of data processing elements;
an intermediate memory connected to at least some of the elements;
a Memory Management Unit (MMU); and
an interface unit between the intermediate memory and a higher level memory;
wherein the intermediate memory is adapted to buffer data pages of the higher memory.
23 . The processor arrangement according to claim 22 , further comprising:
a bus system for transferring data between at least one of any of the data processing and memory elements and any other of the data processing and memory elements, the bus system being adapted for dynamically establishing and releasing point-to-point connects between a sending element and a receiving element.
24 . The processor arrangement according to claim 22 , wherein the intermediate memory has an associated address translation table.
25 . The processor arrangement according to claim 24 , wherein the address translation table is a Translation Lookaside Buffer (TLB).
26 . The processor arrangement according to claim 22 , wherein the higher memory is external to the chip.
27 . The processor arrangement according to claim 22 , further comprising:
an arrangement to move data pages from the higher memory to the intermediate memory if a respective address is accessed.
28 . The processor arrangement according to claim 22 , further comprising:
an arrangement to move data pages from the higher memory to the intermediate memory if a page fault occurs.
29 . The processor arrangement according to claim 22 , further comprising:
an arrangement to translate a virtual address into a physical address of the intermediate memory.
30 . The processor arrangement according to claim 22 , further comprising:
an arrangement to unload pages from the intermediate memory to the higher memory.
31 . The processor arrangement according to claim 22 , further comprising:
an arrangement to unload pages from the intermediate memory to the higher memory if the intermediate memory has no space to store additional new pages.
32 . The processor arrangement according to claim 22 , further comprising:
an address translation table for translating virtual addresses into physical addresses of the intermediate memory.
33 . The processor arrangement according to claim 22 , wherein the address translation table is a Translation Lookaside Buffer (TLB).
34 . The processor arrangement according to claim 22 , further comprising:
an address translation table associated with the local memory issuing a Page Fault in case a page is not stored in the intermediate memory.
35 . The processor arrangement according to claim 34 , wherein the address translation table is a Translation Lookaside Buffer (TLB).