Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
View Patent ↗A method of caching commands in microprocessors having a plurality of arithmetic units and in modules having a two- or multidimensional cell arrangement is provided. The method includes combining a plurality of cells and arithmetic units to form a plurality of groups, assigning a cache unit to a group, and connecting the cache unit to a higher level unit via a tree structure. The cache unit may send requests for required commands to the higher level cache unit, which may return a command sequence including the required command, if the higher level cache unit holds the first command sequence including the required command in the higher level cache unit's local memory.
1. A method for reconfiguring a multi-dimensional configurable cell arrangement, comprising:
transmitting a new reconfiguration instruction by a reconfiguration unit to at least one of a plurality of reconfigurable cells, wherein the reconfiguration unit has a memory for storing reconfiguration instructions for cells that are in a non-reconfigurable state, and wherein the reconfiguration unit transmits the new reconfiguration instruction to the at least one cell upon a condition that a reconfiguration instruction for the at least one cell is not stored in the memory;
in response to the new reconfiguration instruction:
reconfiguring the at least one cell according to the new reconfiguration instruction if the at least one cell is in a reconfigurable state; and otherwise
transmitting reject information by the at least one cell to the unit; and
in response to the reject information, storing the new reconfiguration instruction in the memory.