Logic cell array and bus system
View Patent ↗A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.
1. A data processor on a chip comprising:
a plurality of data processing cores, each of at least some of the processing cores including:
at least one arithmetic logic unit that supports at least division and multiplication of at least 32-bit wide data; and
at least 3 registers for storing at least 32-bit wide data;
a plurality of memory units to buffer at least 32-bit wide data;
at least one interface unit for providing at least one communication channel between the data processor and external memory; and
a bus system flexibly interconnecting the plurality of processing cores, the plurality of memory units, and the at least one interface;
wherein:
the bus system includes a first structure dedicated for data transfer in a first direction and a second structure dedicated for data transfer in a second direction; and
each of at least some of the data processing cores includes a physically dedicated connection to at least one physically assigned one of the plurality of memory units, the assigned one of the plurality of memory units being accessible by another of the data processing cores via a secondary bus path of the bus system.
2. The data processor according to claim 1 , wherein the at least one secondary bus path includes respective dedicated structures for each of two directions of data transfer.
3. The data processor according to any one of claims 1 and 2 , wherein the at least one secondary bus path comprises at least one pipeline register for transferring data.
4. The data processor according to any one of claims 1 and 2 , wherein the at least one secondary bus path comprises at least one first-in-first-out (FIFO) buffer for transferring data.
5. The data processor according to any one of claims 1 and 2 , wherein the bus system supports transmission of at least 64-bit wide data.
6. The data processor according to any one of claims 1 and 2 , wherein the bus system transfers data using a bus protocol.
7. The data processor according to any one of claims 1 and 2 , wherein the bus system uses protocol signals for controlling the data transfer.
8. The data processor according to any one of claims 1 and 2 , further comprising at least one additional data processing core whose internal architecture is different than each of the plurality of data processing cores.
9. The data processor according to claim 8 , wherein the at least one additional data processing core is connectable to at least one of the plurality of memory units only via at least one secondary bus path shared with one or more of the plurality of data processing cores.
10. The data processor according to any one of claims 1 and 2 , wherein the at least one interface unit includes at least two interface units, and the at least one communication channel includes a respective communication channel for each of the at least two interface units.
11. The data processor according to any one of claims 1 and 2 , wherein the at least one interface unit transfers data between the data processor and external memory in packets.
12. The data processor according to any one of claims 1 , 2 and 11 , wherein the at least one interface unit supports a plurality of data processor internal data channels.
13. The data processor according to claim 12 , wherein the at least one interface unit sorts data received from external memory to provide them to the internal channels.
14. The data processor according to any one of claims 1 and 2 , wherein each of at least some of the data processing cores includes at least 8 registers for storing at least one of (a) at least 32-bit wide data and (b) at least 32-bit wide control information.
15. The data processor according to any one of claims 1 and 2 , wherein each secondary bus path increases a latency of the data transmission.
16. A data processor on a chip comprising:
a plurality of data processing cores, each of at least some of the processing cores including:
at least one arithmetic logic unit that supports at least division and multiplication of at least 32-bit wide data; and
at least 3 registers for storing at least 32-bit wide data;
a plurality of memory units to buffer at least 32-bit wide data;
at least one interface unit for providing at least one communication channel between the data processor and external memory; and
a bus system flexibly interconnecting the plurality of processing cores, the plurality of memory units, and the at least one interface;
wherein:
the bus system includes a first structure dedicated for data transfer in a first direction and a second structure dedicated for data transfer in a second direction; and
each of at least some of the data processing cores includes a dedicated connection to at least one assigned one of the plurality of memory units each situated such that no other data processing core and no other memory unit is positioned between the respective data processing core and the respective assigned memory unit, the assigned one of the plurality of memory units being accessible by another of the data processing cores via a secondary bus path of the bus system.
17. The data processor according to claim 16 , wherein the at least one secondary bus path includes respective dedicated structures for each of two directions of data transfer.
18. The data processor according to any one of claims 16 and 17 , wherein the at least one secondary bus path comprises at least one pipeline register for transferring data.
19. The data processor according to any one of claims 16 and 17 , wherein the at least one secondary bus path comprises at least one first-in-first-out (FIFO) buffer for transferring data.
20. The data processor according to any one of claims 16 and 17 , wherein the bus system supports transmission of at least 64-bit wide data.
21. The data processor according to any one of claims 16 and 17 , wherein the bus system transfers data using a bus protocol.
22. The data processor according to any one of claims 16 and 17 , wherein the bus system uses protocol signals for controlling the data transfer.
23. The data processor according to any one of claims 16 and 17 , further comprising at least one additional data processing core whose internal architecture is different than each of the plurality of data processing cores.
24. The data processor according to claim 23 , wherein the at least one additional data processing core is connectable to at least one of the plurality of memory units only via at least one secondary bus path shared with one or more of the plurality of data processing cores.
25. The data processor according to any one of claims 16 and 17 , wherein the at least one interface unit includes at least two interface units, and the at least one communication channel includes a respective communication channel for each of the at least two interface units.
26. The data processor according to any one of claims 16 and 17 , wherein the at least one interface unit transfers data between the data processor and external memory in packets.
27. The data processor according to any one of claims 16 , 17 , and 26 , wherein the at least one interface unit supports a plurality of data processor internal data channels.
28. The data processor according to claim 27 , wherein the at least one interface unit sorts data received from external memory to provide them to the internal channels.
29. The data processor according to any one of claims 16 and 17 , wherein each of at least some of the data processing cores includes at least 8 registers for storing at least one of (a) at least 32-bit wide data and (b) at least 32-bit wide control information.
30. The data processor according to any one of claims 16 and 17 , wherein each secondary bus path increases a latency of the data transmission.