Multi-processor bus and cache interconnection system

1. A system, the system comprising:

a processing system comprising

a plurality processors; and

at least one separated cache not part of any processor;

a bus system connecting the processing system to one or more external devices;

at least one interface transmitting data between the processing system and external devices via the bus system;

at least some of the plurality of processors, the at least one interface, and the at least one separated cache having a module identification (ID); and wherein

the at least one interface to transmit data via the bus system using a protocol, comprising:

i. the module ID of an interface, a processor, a separated cache requesting a transmission,

ii. the module ID of an interface, a processor, a separated cache receiving a transmission; and/or

iii. the address of a target within the interface, the processor, the separated cache or the external device unit receiving a transmission; and

wherein the module ID is defined by a configuration unit.

2. The system of claim 1 , further including multiplexers responsive to module IDs.

3. The system of claim 2 , further including decoders connected to the multiplexors, the decoders being responsive to both the module IDs of a target and to addresses within a target.

4. A system, the system comprising:

a processing system comprising

a plurality of processors; and

at least one separated cache not part any processor;

a bus system connecting the processing system to one or more external devices;

at least one interface transmitting data between the processing system and external devices via the bus system;

at least some of the plurality of processors, the at least one interface, and the at least one separated cache having a module identification (ID); and wherein

the at least one interface to transmit data via the bus system using a protocol, comprising:

i. the module ID of an interface, a processor, a separated cache requesting a transmission,

ii. the module ID of an interface, a processor, a separated cache receiving a transmission; and/or

iii. the address of a target within the interface, the processor, the separated cache or the external device unit receiving a train mission; and

wherein the at least one separated cache comprises a separated cache segment for at least some of the plurality of processors; the system further comprising:

an interconnect system interconnecting each of the separated cache segments with each of the processors, each of the processors with neighboring processors, and each of the separated cache segments with neighboring separated cache segments; and

an arbiter, the arbiter controlling access of a processor to the interconnect system.

5. The bus system of claim 4 where the arbiter is operable to allow processor access in chronological sequence.

6. A system, the system comprising:

a processing system comprising

a plurality of processors; and

at least one separated cache not part of any processor;

a bus system connecting the processing system to one or more external devices;

at least one interface transmitting data between the processing system and external devices via the bus system;

at least some of the plurality of processors, the at least one interface, and the at least one separated cache having a module identification (ID); and wherein

the at least one interface to transmit data via the bus system using a protocol, comprising:

i. the module ID of an interface, a processor, a separate cache requesting a transmission,

ii. the module ID of an interface, a processor, a separated cache receiving a transmission; and/or

iii. the address of a target within the interface, the processor, the separated cache or the external device unit receiving a transmission; and

wherein the at least one interface comprises a buffer memory; the buffer memory having three associated pointers:

i. a first pointer to point to the buffer location from which data is output from the buffer;

ii. a second pointer to point the buffer location to which data is input to the buffer; and

iii. a third pointer to store the value of the first pointer at the start of a data transfer;

wherein the at least one interface is to

i. store transfer data in the buffer memory;

ii. transmit data to a selected to one of said external devices;

iii. receive from the selected one of said external devices transmitting information as to whether a data transfer was successful or has failed;

iv. if the information indicates that a data transfer has failed, repeat the data transfer from buffer position indicated by the third pointer.

7. A system, the system comprising:

a processing system comprising

a plurality of processors; and

at least one separated cache not part of any processor;

a bus system connecting the processing system to one or more external devices;

at least one interface transmitting data between the processing system and external devices via the bus system;

at least some of the plurality of processors, the at least one interface, and the at least one separated cache having a module identification (ID); and wherein

the at least one interface to transmit data via the bus system using a protocol, comprising:

i. the module ID of an interface, a processor, a separate cache requesting a transmission,

ii. the module ID of an interface, a processor, a separated cache receiving a transmission; and/or

iii. the address of a target within the interface, the processor, the separated cache or the external device unit receiving a transmission; and

wherein said at least one interface is to store and transmit data to external devices in packets via a buffer memory.

8. A system, the system comprising:

a processing system comprising

a plurality of processors; and

at least one separated cache not part of any processor;

a bus system connecting the processing system to one or more external devices;

at least one interface transmitting data between the processing system an external devices via the bus system;

at least some of the plurality of processors, the at least one interface, and the at least one separated cache having a module identification (ID); and wherein

the at least one interface to transmit data via the bus system using a protocol comprising:

i. the module ID of an interface, a processor, a separated cache requesting a transmission,

ii. the module ID of an interface, a processor, a separated cache receiving a transmission; and/or

iii. the address of a target within the interface, the processor, the separated cache or the eternal device unit receiving a transmission; and

wherein the at least one interface is further to generate time stamps that are transmitted with data transfers.

9. The system according to claim 8 , wherein the time stamps are unique.

10. A system, the system comprising:

a processing system comprising

a plurality of processors; and

at least one separated cache not part of any processor;

a bus system connecting the processing system to one or more external devices;

at least one interface transmitting data between the processing system and external devices via the bus system;

at least some of the plurality of processors, the at least one interface, and the at least one separated cache having a module identification (ID); and wherein

the at least one interface to transmit data via the bus system using a protocol, comprising:

i. the module ID of an interface, a processor, a separated cache requesting a transmission,

ii. the module ID of an interface, a processor, a separated cache receiving a transmission; and/or

iii. the address of a target within the interface, the processor, the separated cache or the external device unit receiving a transmission; and

wherein the bus system is operable to transmit interrupt requests.