Multi-processor with selectively interconnected memory units
View Patent ↗A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.
1. A multi-processor, comprising:
a plurality of data processing units, each comprising an arithmetic logic unit;
at least some of the plurality of data processing units forming a multi-processor;
a plurality of memory units; and
a bus system selectively interconnecting the plurality of data processing units and the plurality of memory units; and
further at least one of the processing units forming a load unit to transmit a program part to be executed to the plurality of memory units.
2. The multi-processor according to claim 1 , wherein the data processing unit comprises a decoder.
3. The multi-processor according to claim 1 , further comprising at least one input-output (I/O) unit, wherein the bus system selectively interconnects at least one of said plurality of processor units, at least one of said plurality of memory units, and at least one of said I/O unit.
4. The multi-processor according to claim 1 , wherein one or more of said processing units are connected to at least two clock sources having different clock frequencies.
5. The multi-processor according to claim 1 , further including a Memory Management Unit (MMU).
6. The multi-processor according to claim 1 , wherein the bus system further selectively interconnects processing units with each other.
7. A multi-processor, comprising:
a plurality of data processing units, each comprising an arithmetic logic unit;
a plurality of memory units; and
a bus system selectively interconnecting the plurality of data processing units and the plurality of memory units; wherein the input-output (I/O) unit is configured as a Memory Management Unit (MMU).
8. The multi-processor according to claim 7 , wherein the data processing unit comprises a decoder.
9. The multi-processor according to claim 7 , further comprising at least one input-output (I/O) unit, wherein the bus system selectively interconnects at least one of said plurality of processor units, at least one of said plurality of memory units, and at least one of said I/O unit.
10. The multi-processor according to claim 7 , wherein one or more of said processing units are connected to at least two clock sources having different clock frequencies.
11. The multi-processor according to claim 7 , further including a Memory Management Unit (MMU).
12. The multi-processor according to claim 7 , wherein the bus system further selectively interconnects processing units with each other.