Stacked-die multi-processor
View Patent ↗A plurality of stacked dies has outer dies that permits high heat dissipation. A plurality of processors is located on a first outer die. A plurality of memory elements located on a second outer die. An interconnect structure is located an inner die.
1. A multi-processor device, comprising:
a plurality of data processing cores on a first die;
a plurality of memory elements on at least a second die;
an interconnection network interconnecting the first and at least second die, the interconnection network located on a third die.
2. An integrated device, comprising:
three stacked dies comprising, lower, middle and top dies;
a plurality of processors on the lower die;
a plurality of memory elements on the top die; and
an interconnection network on the middle die.
3. The integrated device of claim 2 , wherein the top die has higher heat dissipation than the middle and lower dies.
4. A processor system, comprising:
a plurality of stacked dies having a first outer die and a second outer die that each permit high heat dissipation, and at least one inner die that has low heat dissipation;
a plurality of processors located on the first outer die;
a plurality of memory elements located on the second outer die; and
an interconnect structure located on the at least one inner die.