Data processor chip with flexible bus system
View Patent ↗A data processor chip having a two-dimensional array of arithmetic logic units and memory where the arithmetic logic units are in communication with memory units in one dimension and with other arithmetic units in a second.
1. A data processor on a chip comprising:
an array of processing units, wherein a processing unit comprises either an arithmetic logic unit operative to perform one or more of a plurality of arithmetic operand functions or a memory unit, wherein a first axis of the array of processing units comprises at least one arithmetic logic unit in communication with at least one memory unit;
at least one interface unit operative to provide at least one communication channel between the data processor and an external memory;
a bus system flexibly interconnecting the array of processing units for multi-directional communication across the bus system among the array of processing units.
2. The data processor of claim 1 , wherein the array is a two dimensional array, the first axis being a horizontal axis and a second axis, the second axis being a vertical axis.
3. The data processor of claim 1 , wherein the array is a three dimensional array, the first axis being different from a second axis, the first axis and the second axis each being at least one of an X axis, a Y axis and a Z axis.
4. The data processor of claim 1 , wherein the bus system includes:
a first structure dedicated for data transfer in the first axis; and
a second structure dedicated for data transfer in a second axis.
5. The method of claim 4 , wherein the bus system further includes at least one secondary bus path providing communication between a plurality of the processing units.
6. The method of claim 5 , wherein the at least one secondary bus path comprises at least one first-in-first-out buffer for transferring data.
7. The method of claim 1 , wherein the bus system supports transmission of at least 32-bit wide data.
8. The method of claim 1 , wherein the bus system supports transmission of at least 64-bit wide data.
9. The method of claim 1 , wherein the at least one interface unit transfers data between the data processor and an external memory in packets.
10. The method of claim 1 , wherein the at least one interface unit supports a plurality of data processor internal data channels.
11. A data processor on a chip comprising:
a plurality of processing array units disposed in a multidimensional array, wherein a processing array unit comprises either an arithmetic logic unit operative to perform one or more of a plurality of arithmetic operand functions or a memory unit, and wherein at least one memory unit is in operative communication with a plurality of arithmetic logic units;
at least one interface unit operative to provide at least one communication channel between the plurality of processing units;
a bus system flexibly interconnecting the plurality of processing array units for multi-directional communication across the bus system among the plurality of processing array units.