Multi-processor with selectively interconnected memory units

1. A multi-processor, comprising:

a plurality of data processors, each data processor comprising:

an arithmetic logic unit having an ALU data output and an ALU data input;

an instruction decoder; and

a local random access memory (RAM) having a RAM data output and a RAM data input; wherein

the ALU data output is connected to the RAM data input; and further wherein

the RAM data output is connected to the ALU data input;

a plurality of edge memories; and

a bus system selectively interconnecting the plurality of data processors and the plurality of edge memories.

2. The multi-processor according to claim 1 , further comprising at least one input-output (I/O) processor, wherein the bus system selectively interconnects at least one of said plurality of data processor units, at least one of said plurality of edge memories, and at least one of said I/O processor.

3. The multi-processor according to claim 1 , wherein one or more of said data processors are connected to at least two clock sources having different clock frequencies.

4. The multi-processor according to claim 1 , further including an instruction loader, the instruction loader to transmit a program part, comprising one or more ALU instructions, to the local memories of said plurality of data processors.

5. The multi-processor according to claim 1 , further including a Memory Management Unit (MMU).

6. The multi-processor according to claim 2 , wherein the input-output (I/O) unit is configured as a Memory Management Unit (MMU).

7. The multi-processor according to claim 1 , wherein the bus system further selectively interconnects processors with each other.