Methods and devices for treating and processing data
A method of clocking a plurality of programmable, sequential data processing units, by adjusting the clock frequency of at least one of the programmable, sequential data processing units, without affecting the clock frequency of at least one other of the programmable, sequential data processing units.
1. A method of processing data in a multicore processor, the multicore processor including a plurality of programmable data processing units that each (a) is adapted for clocked data processing and (b) includes at least one respective Arithmetic Logic Unit (ALU), the method comprising, at runtime:
determining that a first one of a plurality of implementable clock frequencies is to be implemented for data processing by a first one of the plurality of programmable data processing units, wherein the first clock frequency is slower than a maximum one of the plurality of implementable clock frequencies, wherein the multicore processor includes a plurality of clock multipliers via which a base clock frequency is convertible into respective different ones of the plurality of implementable clock frequencies that are different than the base clock frequency, which correspond to respective division ratios; and
based on the determination:
generating, by one of the clock multipliers and using the base clock frequency, a local clock whose first clock rate is at the determined first one of the plurality of implementable clock frequencies; and
under control of the local clock generated by the one of the clock multipliers, performing, by the first programmable data processing unit, the data processing at the first clock rate, while a second one of the plurality of programmable data processing units processes data under influence of a second one of the plurality of clock multipliers, at a second clock rate that is set by the second clock multiplier at a second one of the implementable clock frequencies that is higher than the first one of the plurality of implementable clock frequencies.
2. The method of claim 1 , wherein data is processed sequentially via the data processing by the first data processing unit.
3. The method of claim 1 , wherein the data processing by each of the first and second data processing units is a sequential data processing.
4. The method of claim 1 , wherein the determination of the first clock frequency is made based on a task execution priority.
5. The method of claim 1 , wherein the determination of the first clock frequency is made based on a drop in a supplied voltage.
6. The method of claim 1 , wherein the determination of the first clock frequency is made based on a temperature.
7. The method of claim 1 , wherein the determination of the first clock frequency is made based on a task execution priority and a drop in a supplied voltage.
8. The method of claim 1 , wherein the determination of the first clock frequency is made based on a task execution priority and a temperature.
9. The method of claim 1 , wherein the determination of the first clock frequency is made based on a drop in a supplied voltage and a temperature.
10. The method of claim 1 , wherein the determination of the first clock frequency is made based on a task execution priority, a drop in a supplied voltage, and a temperature.
11. The method of claim 1 , wherein the multicore processor includes for each of the plurality of programmable data processing units, a respective sensor for sensing a voltage that is supplied.
12. The method of claim 1 , further comprising sensing by a sensor associated with the first programmable data processing unit a supplied voltage associated with the first programmable data processing unit, wherein the determination of the first clock frequency is made based on the sensed voltage.
13. The method of claim 1 , further comprising sensing respective temperatures at each of a plurality of regions, wherein the determination of the first clock frequency is made based on one of the sensed temperatures which is of one of the plurality of regions in which the first programmable data processing unit is located.
14. The method of claim 1 , wherein the first clock frequency is a reduced frequency to which a rate of operation of the first programmable data processing unit has been reduced, and the method further comprises, responsive to a subsequent sensing of a rise in temperature, further reducing the rate of operation of the first programmable data processing unit to an even lower frequency.
15. The method of claim 1 , wherein:
the multicore processor is part of a mobile device having, as a voltage source, a battery of exhaustible capacity; and
the determination of the first clock frequency is a determination to lower the cock rate of the first programmable data processing unit in response to a determination that an energy reserve of the battery is low.
16. The method of claim 1 , wherein each of the plurality of clock multipliers is programmable for setting a plurality of the plurality of implementable clock frequencies at different times.