IP Library Granted Patent US 7,923,804
Granted Patent B2
US 7,923,804 · App. 12/367,716 · Granted Apr 12, 2011

Edge termination with improved breakdown voltage

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Quick Facts
Patent No.
US 7,923,804
App. No.
12/367,716
Granted
Apr 12, 2011
Kind
B2
Abstract

A MOSFET switch which has a low surface electric field at an edge termination area, and also has increased breakdown voltage. The MOSFET switch has a new edge termination structure employing an N-P-N sandwich structure. The MOSFET switch also has a polysilicon field plate configuration operative to enhance any spreading of any depletion layer located at an edge of a main PN junction of the N-P-N sandwich structure.

Claims (30)

1. A semiconductor device, comprising:

one or more active device segments;

an edge termination structure, surrounding one or more of said active device segments; and

multiple trench field plates, successively surrounding said edge termination and each other;

wherein ones of said field plates are embedded in respective trenches, and wherein respective concentrations of a compensating dopant lie beneath said trenches.

2. The device of claim 1 , wherein an additional field plate, which is not embedded in a trench, also surrounds one or more of said trench field plates.

3. The device of claim 1 , wherein said active device segments include vertical field-effect transistors.

4. The device of claim 1 , wherein said active device segments also include recessed field plates intermingled with active devices, and said recessed field plates also have compensating dopant concentrations thereunder.

5. The device of claim 1 , wherein said active device segments also include recessed field plates intermingled with active devices, and said recessed field plates also have compensating dopant concentrations thereunder; and wherein said recessed field plates in said active device segments have the same characteristics as one or more of said trench field plates.

6. The device of claim 1 , wherein multiple ones of said trench field plates are electrically floating.

7. The device of claim 1 , wherein said respective concentrations of a compensating dopant, under multiple ones of said trench field plates, are heavy enough to invert the conductivity type of material thereunder.

8. The device of claim 1 , wherein said respective concentrations of a compensating dopant, under multiple ones of said trench field plates, are outdiffused far enough to mutually overlap.

9. The device of claim 1 , further comprising at least one non-trench field plate inboard of said trench field plates.

10. The device of claim 1 , wherein said active device segments include a body junction which extends into some, but not all, of said termination.

11. The device of claim 1 , wherein said active device segments and said termination are constructed in epitaxial semiconductor material.

12. The device of claim 1 , further comprising a transition zone, between the active device segments and said edge termination structure.

13. A semiconductor device, comprising:

one or more active device segments having a body junction therein;

an edge termination structure, surrounding one or more of said active device segments, and including a sandwich structure having back-to-back junctions, of which one is approximately coplanar with said body junction; and

one or more field plates, capacitively coupled to said edge termination structure.

14. The device of claim 13 , wherein said sandwich structure includes a p-type middle layer between n-type layers.

15. The device of claim 13 , wherein said body junction is less than 0.5 micron deep.

16. The device of claim 13 , comprising a plurality of said field plates.

17. A method of operating a power semiconductor device, comprising the actions of:

a) providing a desired current characteristic using one or more active device segments; while also simultaneously

b) avoiding edge breakdown by using an edge termination structure, surrounding one or more of said active device segments, and multiple trench field plates, successively surrounding said edge termination and each other;

wherein ones of said field plates are embedded in respective trenches, and wherein respective concentrations of a compensating dopant lie beneath said trenches.

18. The method of claim 17 , wherein an additional field plate, which is not embedded in a trench, also surrounds one or more of said trench field plates.

19. The method of claim 17 , wherein said active device segments include vertical field-effect transistors.

20. The method of claim 17 , wherein said active device segments also include recessed field plates intermingled with active devices, and said recessed field plates also have compensating dopant concentrations thereunder.

Assignments (3)
SECURITY INTEREST Recorded Dec 27, 2022
From: MAXPOWER SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 062228/0648 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2010
From: ZENG, JUN; DARWISH, MOHAMED N.; SU, SHIH-TZUNG
To: MAXPOWER SEMICONDUCTOR INC.
Reel/Frame 024743/0186 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2009
From: ZENG, JUN; DARWISH, MOHAMED N.; SU, SHIH-TZUNG
To: MAXPOWER SEMICONDUCTOR INC.
Reel/Frame 022598/0108 →