Thyristor-based memory and its method of operation
A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of the adaptive bias may change with respect to temperature and may influence and/or compensate an inherent bipolar gain of the thyristor in accordance with the change in bias and may enhance its performance and/or reliability over a range of operating temperature. In a particular embodiment, the thyristor may be formed in a layer of silicon of an SOI substrate and the adaptive bias coupled to a supporting substrate of the SOI structure.
1. A semiconductor memory comprising:
an access transistor comprising a gateable channel;
a capacitively-coupled thyristor memory cell accessible via the access transistor;
the capacitively-coupled thyristor memory cell comprising a gate electrode disposed over a base region of the thyristor; and
a temperature sensing circuit to sense temperature and coupled to affect a voltage of the gate electrode based on the temperature sensed;
wherein the capacitively-coupled thyristor memory cell is formed in a silicon layer of a silicon-on-insulator (“SOI”) substrate structure; and
wherein the temperature sensing circuit is coupled to define a voltage level of the capacitor electrode relative to that of a support substrate of the SOI substrate structure located below the silicon layer.
2. A circuit comprising:
a plurality of memory cells; and
at least one memory cell of the plurality of memory cells comprising:
a thyristor having an anode emitter region, an N-base region, a P-base region;
a gate electrode disposed over one of the N-base region and the P-base region; and
a variable source coupled to bias the gate electrode with a voltage level;
wherein the bias provided by the variable source changes responsive to changes in temperature; and
wherein the variable source biases the gate electrode with the voltage level which is further responsive to voltage of a support body of the thyristor.
3. The circuit of claim 2 , further comprising another variable source coupled to bias the support body responsive to changes in temperature.
4. A circuit comprising:
a plurality of memory cells; and
at least one memory cell of the plurality of memory cells comprising:
a thyristor having an anode emitter region, an N-base region, a P-base region, and a cathode-emitter region;
a gate electrode disposed over one of the N-base region and the P-base region; and
a variable source coupled to bias the gate electrode with a voltage level;
wherein the bias provided by the variable source changes responsive to changes in temperature; and
wherein the variable source is configured to change the voltage level of the gate electrode relative to voltage of a supporting substrate located beneath the thyristor.
5. A circuit comprising:
a plurality of memory cells; and
at least one memory cell of the plurality of memory cells comprising:
a thyristor having an anode emitter region, an N-base region, a P-base region, and a cathode-emitter region;
a gate electrode disposed over one of the N-base region and the P-base region; and
a variable source coupled to bias the gate electrode with a voltage level;
wherein the bias provided by the variable source changes responsive to changes in temperature;
wherein the thyristor comprises a bipolar transistor;
wherein the bipolar transistor comprises an intrinsic gain-versus-temperature interdependency associated with a positive/negative co-efficient; and
wherein the bias varies with the temperature to influence gain of the bipolar transistor for a negative/positive interrelationship co-efficient component that is opposite the intrinsic gain-versus-temperature interdependency.