Method for fabricating a semiconductor device
View Patent ↗A semiconductor device has a first interlayer insulating film formed on a substrate, having a first interconnection buried therein, and having a depressed portion and an insulating barrier film formed on the first interlayer insulating film. A second interlayer insulating film is formed to fill in the depressed portion, cover the upper surface of the insulating barrier film, and have a second interconnection buried therein.
1. A method for fabricating a semiconductor device, the method comprising the steps of:
(a) forming a first interlayer insulating film on a substrate and then burying at least two first interconnections in the formed first interlayer insulating film;
(b) depositing an insulating barrier film on the first interlayer insulating film;
(c) performing etching with respect to the first interlayer insulating film to form a depressed portion between the first interconnections in the first interlayer insulating film;
(d) depositing a second interlayer insulating film to fill in the depressed portion and cover the insulating barrier film; and
(e) burying a via plug connected electrically to at least one of the first interconnections in the second interlayer insulating film.
2. The method of claim 1 , wherein the step (c) is performed after the step (b) and includes etching the insulating barrier film.
3. The method of claim 2 , wherein, in the step (c), the insulating barrier film is etched by using a dry etching process in which an etching rate is higher for the insulating barrier film than for the first interlayer insulating film and the first interlayer insulating film is etched by using a wet etching process in which the etching rate is higher for the first interlayer insulating film than for the insulating barrier film such that the insulating barrier film is formed to have a portion overhanging the depressed portion and the depressed portion is formed to have a configuration which is wider at an upper end portion thereof than at a bottom surface thereof.
4. The method of claim 3 , wherein, in the step (d), the second interlayer insulating film is filled in a space under the portion of the insulating barrier film overhanging the depressed portion.
5. The method of claim 1 , wherein the step (b) is performed after the step (c) to cover a bottom surface of the depressed portion and a sidewall thereof with the insulating barrier film.
6. The method of claim 1 , wherein each of the first and second interlayer insulating films is a low dielectric constant film.
7. The method of claim 1 , wherein each of the first interconnections and the via plug is composed of a barrier metal film and a copper film.
8. The method of claim 1 , further comprising
a step (f) of forming a second interconnection electrically connected to the via plug in another interlayer insulating film different from the first interlayer insulating film.
9. The method of claim 8 , wherein the step (f) include a step of, after forming a via hole and a second interconnection trench in the second interlayer insulating film, depositing copper so that the via hole and the second interconnection trench is buried on the second interlayer insulating film, and then, polishing copper located outside the second interconnection trench by a chemical mechanical polishing method.
10. The method of claim 1 , wherein the second interconnect including the via plug is formed by a dual damascene method.
11. The method of claim 1 , wherein the second interconnect is formed in the second interlayer insulating film.
12. The method of claim 1 , wherein the insulating barrier film is made of SiC, SiN, SiCN, BCB or CoWB.