Microcomputer with address translation circuit
View Patent ↗A microcomputer includes a first CPU, a first bus, a first memory, a second CPU, a second bus, and a second memory. The first memory and the second memory are arranged in address spaces individually managed by the first CPU and the second CPU corresponding to the memories. An address translation circuit is provided. When a task so programmed to have a data area in the first memory is transferred to the second memory and executed by the second CPU, the address translation circuit carries out the following processing: the address translation circuit translates an address outputted from the second CPU so that access to the first memory by the task becomes access to the second memory. As a result, the number of access cycles is reduced and degradation in computing capability is avoided when a task is transferred between CPUs for load sharing.
1. A microcomputer comprising:
a first CPU capable of processing a predetermined task;
a first bus coupled with the first CPU;
a first memory accessed by the first CPU through the first bus and used as a local memory of the first CPU;
a second CPU capable of processing a predetermined task;
a second bus coupled with the second CPU; and
a second memory accessed by the second CPU through the second bus and used as a local memory of the second CPU,
wherein the first memory and the second memory are arranged in address spaces individually managed by the first CPU and the second CPU corresponding thereto,
wherein the microprocessor further comprises an address translation circuit configured to translate an address output from the second CPU so that access to the first memory by the task becomes access to the second memory when a task so programmed that the task has a data area in the first memory is transferred to the second memory and executed by the second CPU, and
wherein the address translation circuit includes
a first register capable of holding the initial address of each task in the first memory;
a second register capable of holding information on the size of the task;
a third register capable of holding the initial address of each task in the second memory;
a determination unit configured to determine whether or not an address output from the second CPU falls within an address range determined by information held in the first register and information held in the second register; and
a translation unit configured to carry out address translation by adding information held in the third register to the address output from the second CPU when an address output from the second CPU is within the address range.
2. The microcomputer according to claim 1 , further including:
a table storing the address range of a data area with respect to each task,
wherein the table is referred to when a task is executed.
3. The microcomputer according to claim 1 ,
wherein when a task so programmed that the task has a data area in the first memory is processed at the second CPU, the data area in the first memory is copied into the second memory and after the completion of processing of the task at the second CPU, the data area in the first memory is updated with data in the second memory.
4. The microcomputer according to claim 1 , including:
a flag that makes it possible to determine whether the first memory or the second memory holds the latest values in the data area for the task, and
wherein when the executing CPU does not have a valid data area in the local memory thereof, the values in the data area are copied from the local memory of the other CPU to the local memory thereof and after the completion of execution of the task, the flag is changed so that the data area in the local memory thereof is valid.
5. The microcomputer according to claim 2 ,
wherein when a task so programmed that the task has a data area in the first memory is processed by the second CPU, the data area in the first memory is copied into the second memory and after the completion of processing of the task at the second CPU, the data area in the first memory is updated with data in the second memory.
6. The microcomputer according to claim 2 , including:
a flag that makes it possible to determine whether the first memory or the second memory holds the latest values in the data area for the task, and
wherein when the executing CPU does not have a valid data area in the local memory thereof, the values in the data area are copied from the local memory of the other CPU to the local memory thereof and after the completion of execution of the task, the flag is changed so that the data area in the local memory thereof is valid.