Granted Patent B2

US 8,169,839 · App. 12/369,079 · Granted May 1, 2012

Abstract

Claims (28)

1. A memory device for use with a host processor and a primary power source, the memory device comprising:

non-volatile memory;

volatile memory;

an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from the primary power source;

an isolation circuit for controlling access to the volatile memory by the host processor, said isolation circuit having a first mode during which the isolation circuit provides the host processor with access to the volatile memory for storing or reading data and a second mode during which the isolation circuit electrically disconnects the volatile memory from the host processor; and

a controller controlling the isolation circuit, said controller programmed to place the isolation circuit in the first mode when the volatile memory is being powered by the primary power source and, when power to the volatile memory from the primary power source is interrupted, to place the isolation circuit in the second mode and transfer data from the volatile memory to the non-volatile memory,

wherein the isolation circuit comprises a first multiplexer arranged to multiplex address and control signals and a second multiplexer arranged to multiplex data signals.

2. The memory device of claim 1 , wherein the controller is further programmed to

restore data from the non-volatile memory to the volatile memory upon a restoration of the primary power source; and

when the data is restored, place the isolation circuit in the first mode.

3. The memory device of claim 1 , wherein the volatile memory comprises a dynamic random access memory.

4. The memory device of claim 1 , wherein the non-volatile memory comprises electrically erasable programmable read-only memories (EEPROMs).

5. The memory device of claim 1 , wherein the controller comprises at least one of an application-specific integrated circuit (ASIC) and a field programmable gate array (FPGA).

6. The memory device of claim 1 , wherein power from the backup power source is primarily from a capacitor.

7. The memory device of claim 1 , wherein power from the backup power source is primarily from a super capacitor.

8. A method comprising:

detecting a power failure of a primary power source of a volatile memory; and

in response to detecting the power failure and while the volatile memory is powered by a backup power source:

changing a mode of an isolation circuit from a first mode that provides a host processor with access to the volatile memory for storing or reading data when the volatile memory is being powered by the primary power source to a second mode that electrically disconnects the volatile memory from the host processor; and

moving data stored in the volatile memory to a non-volatile memory,

wherein the isolation circuit comprises a first multiplexer arranged to multiplex address and control signals and a second multiplex arranged to multiplex data signals.

9. The method of claim 8 , further comprising:

restoring data from the non-volatile memory to the volatile memory upon a restoration of the primary power source; and

when the data is restored, placing the isolation circuit in the first mode.

10. The method of claim 8 , wherein the volatile memory comprises a dynamic random access memory.

11. The method of claim 8 , wherein the non-volatile memory comprises electrically erasable programmable read-only memories (EEPROMs).

12. The method of claim 8 , wherein power from the backup power source is primarily from a capacitor.

13. The method of claim 8 , wherein power from the backup power source is primarily from a super capacitor.

Assignments (6)