Method of nickel-gold plating and printed circuit board
View Patent ↗Disclosed are a method of electroless nickel-gold plating an object and a printed circuit board. The method in accordance with an embodiment of the present invention includes: forming a first nickel plated layer on a surface of the object; forming a second nickel plated layer on the first nickel plated layer; and forming a gold plated layer on the second nickel plated layer.
1. A method of electroless nickel-gold plating an object, the method comprising:
forming a first nickel plated layer on a surface of the object;
forming a second nickel plated layer on the first nickel plated layer, the second nickel plated layer being electroless nickel plated to be thinner than the first nickel plated layer and formed with nodules that are smaller than a surface of the first nickel plated layer; and
forming a gold plated layer on the second nickel plated layer.
2. The method of claim 1 , wherein the forming of the first nickel plated layer comprises:
adhering a catalyst to the object; and
performing electroless nickel plating on the object.
3. The method of claim 2 , wherein the catalyst comprises palladium (Pd).
4. The method of claim 1 , wherein the forming of the second nickel plated layer comprises:
adhering a catalyst to the first nickel plated layer; and
performing electroless nickel plating on the first nickel plated layer.
5. The method of claim 4 , wherein the catalyst comprises palladium (Pd).
6. The method of claim 1 , further comprising, before the forming of the first nickel plated layer, forming roughness on the surface of the object.
7. A printed circuit board comprising:
a substrate;
a circuit pattern formed on a surface of the substrate;
a first nickel plated layer formed on the circuit pattern;
a second nickel plated layer formed on the first nickel plated layer, the second nickel plated layer being formed to be thinner than the first nickel plated layer by electroless plating and formed with nodules that are smaller than a surface of the first nickel plated layer; and
a gold plated layer formed on the second nickel plated layer.
8. The printed circuit board of claim 7 , wherein a first palladium layer is interposed between the circuit pattern and the first nickel plated layer.
9. The printed circuit board of claim 7 , wherein a second palladium layer is interposed between the first nickel plated layer and the second nickel plated layer.