Differential amplifier and applications thereof
A differential amplifier includes a first pair of differential amplifiers and a second pair of differential amplifiers. These first and second pairs of differential amplifiers are connected between first power rails and are arranged to receive a differential input signal. Third and fourth pairs of differential amplifiers are connected between second rails and also connected to the differential input signal. A current summer sums a first output current of the first pair of differential amplifiers, a second output current of the second pair of differential amplifiers, a third output current of the third pair of differential amplifiers and a fourth output current of a fourth pair of differential amplifiers to produce an output signal.
1. A differential amplifier, comprising:
an amplifier upper half constructed and arranged to operate in a first voltage range;
an amplifier lower half constructed and arranged to operate in a second voltage range;
means for inputting a differential input signal to the upper half and to the lower half; and
a summer for summing outputs of the upper and lower halves,
wherein the upper half is configured to amplify input signal components within a first input signal voltage range and the lower half is configured to amplify input signal components within a second input signal voltage range, and
wherein at least one of the amplifier upper half and the amplifier lower half includes a voltage limiter coupled to a pair of differential amplifiers.
2. A differential amplifier according to claim 1 wherein the upper half comprises:
a P-MOS pair of differential amplifiers; and
an N-MOS pair of differential amplifiers.
3. A differential amplifier according to claim 2 further comprising a voltage follower coupling input signal components to the P-MOS pair of differential amplifiers.
4. A differential amplifier according to claim 2 , wherein the voltage limiter couples input signal components to the N-MOS pair of differential amplifiers.
5. A differential amplifier according to claim 1 wherein the lower half comprises:
a P-MOS pair of differential amplifiers; and
an N-MOS pair of differential amplifiers.
6. A differential amplifier according to claim 5 further comprising a voltage follower coupling input signal components to the P-MOS pair of differential amplifiers.
7. A differential amplifier according to claim 5 , wherein the voltage limiter couples input signal components to the N-MOS pair of differential amplifiers.
8. A differential amplifier, comprising:
a first pair of differential amplifiers and a second pair of differential amplifiers, the first pair of differential amplifiers and the second pair of differential amplifiers being connected between first rails and configured to receive a differential input signal;
a third pair of differential amplifiers and a fourth pair of differential amplifiers, the third pair of differential amplifiers and the fourth pair of differential amplifiers being connected between second rails and configured to receive the differential input signal;
a current summer for summing a first output current of the first pair of differential amplifiers, a second output current of the second pair of differential amplifiers, a third output current of the third pair of differential amplifiers and a fourth output current of the fourth pair of differential amplifiers to produce an output signal; and
a voltage limiter connected between one of the first and second rails and configured to receive the differential input signal.
9. The differential amplifier of claim 8 , wherein
the first rails comprises a first rail and a second rail;
the second rails comprises a third rail and a fourth rail; and
the differential amplifier is configured to operate with a voltage on first rail that is higher than the voltage on the second rail and a voltage on the third rail that is higher than a voltage on the fourth rail.
10. The differential amplifier of claim 8 , further comprising a voltage follower connected between the first rails and configured to receive the differential input signal and provide an output to the first pair of differential amplifiers.
11. The differential amplifier of claim 8 , wherein the voltage limiter is a high voltage limiter connected between the first rails and configured to provide an output to the second pair of differential amplifiers.
12. The differential amplifier of claim 8 , wherein the voltage limiter is a low voltage limiter connected between the second rails and configured to provide an output to the third pair of differential amplifiers.
13. The differential amplifier of claim 8 further comprising a voltage follower connected between the second rails and configured to receive the differential input signal and provide an output to the fourth pair of differential amplifiers.
14. The differential amplifier of claim 8 , wherein the first pair of differential amplifiers comprises P-MOS transistors.
15. The differential amplifier of claim 8 , wherein the second pair of differential amplifiers comprises N-MOS transistors.
16. The differential amplifier of claim 8 , wherein the third pair of differential amplifiers comprises P-MOS transistors.
17. The differential amplifier of claim 8 , wherein the fourth pair of differential amplifiers comprises N-MOS transistors.
18. A method for amplifying an input differential signal comprising:
passing the input differential signal to an input of a first pair of pair of differential amplifiers and to an input of a second pair of pair of differential amplifiers;
amplifying the input differential signal in the first pair of pair of differential amplifiers when the input differential signal exceeds a specified voltage;
amplifying the input differential signal in the second pair of pair of differential amplifiers when the input differential signal is less than the specified voltage;
protecting the first pair of pair of differential amplifiers and the second pair of pair of differential amplifiers against voltage overstress; and
summing an output of the first pair of pair of differential amplifiers and the output of the second pair of pair of differential amplifiers to produce an output signal.
19. The method of claim 18 , wherein the summing comprises summing currents produced in the first pair of pair of differential amplifiers and currents produced in the second pair of pair of differential amplifiers.
20. An article of manufacture including a non-transient computer-readable storage device having instructions stored therein and comprising executable instructions that when executed by a computing device cause it to become configured to amplify an input differential signal by:
passing the input differential signal to an input of a first pair of pair of differential amplifiers and to an input of a second paid of pair of differential amplifiers;
amplifying the input differential signal in the first pair of pair of differential amplifiers when the input differential signal exceeds a specified voltage;
amplifying the input differential signal in the second pair of pair of differential amplifiers when the input differential signal is less than the specified voltage;
protecting the first pair of pair of differential amplifiers and the second pair of pair of differential amplifiers against voltage overstress; and
summing an output of the first pair of pair of differential amplifiers and the output of the second pair of pair of differential amplifiers to produce an output signal.
21. The article of manufacture of claim 20 , wherein the instructions are programmed in a hardware description language selected from the group consisting of HDL, VHDL and RTL.
22. An article of manufacture including a non-transient computer-readable storage device having instructions stored therein and comprising executable instructions that if executed by a computing device cause it to become configured as a differential amplifier comprising:
a first pair of differential amplifiers and a second pair of differential amplifiers, the first pair of differential amplifiers and the second pair of differential amplifiers being connected between first rails and configured to receive a differential input signal;
a third pair of differential amplifiers and a fourth pair of differential amplifiers, the third pair of differential amplifiers and the fourth pair of differential amplifiers being connected between second rails and configured to receive the differential input signal;
a first voltage limiter coupled to the second pair of differential amplifiers and a second voltage limiter coupled to the third pair of differential amplifiers; and
a current summer for summing a first output current of the first pair of differential amplifiers, a second output current of the second pair of differential amplifiers, a third output current of the third pair of differential amplifiers, and a fourth output current of the fourth pair of differential amplifiers to produce an output signal.
23. The article of manufacture of claim 22 , wherein the instructions are programmed in a hardware description language selected from the group consisting of HDL, VHDL and RTL.