IP Library Granted Patent US 7,948,095
Granted Patent B2
US 7,948,095 · App. 12/369,429 · Granted May 24, 2011

Semiconductor package and method of making the same

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Quick Facts
Patent No.
US 7,948,095
App. No.
12/369,429
Granted
May 24, 2011
Kind
B2
Abstract

The present invention relates to semiconductor devices comprising two or more dies stacked vertically on top of one another, and methods of making the semiconductor devices. The methods may comprise a combination of wafer-level through silicon interconnect fabrication and wafer-level assembly processes.

Claims (17)

1. A semiconductor package comprising:

a substrate;

a first die having a front side, a back side, and a plurality of through silicon interconnects, the first die being stacked onto the substrate; and

a second die having a front side, a back side, and a first plurality of conductive bumps formed at the back side of the second die, the second die being stacked onto the first die and having under-filled the first plurality of conductive bumps such that the first plurality of conductive bumps electrically communicate with the through silicon interconnects;

wherein a first mold material encapsulates the second die and the front side of the first die; and

a second mold material encapsulates the first die, the second die, and a plurality of solder interconnects.

2. The semiconductor package of claim 1 , wherein each of the through silicon interconnects further comprises:

an end portion at the back side of the first die and a top portion at the front side of the first die;

a dielectric layer formed along internal walls of the through silicon interconnect;

a barrier metal layer formed over the dielectric layer;

a seed layer formed over the barrier metal layer; and

a metallic material filling space within the internal walls of the through silicon interconnect.

3. The semiconductor package of claim 2 , further comprising:

a metallic layer and a passivation layer formed on the front side of the first die so as to be non-overlapping;

a metallic layer and a passivation layer formed on the back side of the first die so as to be non-overlapping;

a plurality of under bump metallization (UBM) pads formed on the metallic layer on the back side of the first die; and

a second plurality of conductive bumps formed on the UBM pads.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE INCLUDE PATENT NUMBER 8816482 PREVIOUSLY RECORDED AT REEL: 039885 FRAME: 0541. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 25, 2017
From: UNITED TEST AND ASSEMBLY CENTER LIMITED
To: UTAC HEADQUARTERS PTE. LTD.
Reel/Frame 043979/0820 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO ADD THE ANNEX A AND THE ANNEX B WHICH WAS INADVERTENTLY LEFTOUT IN THE ORIGINAL ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED ON REEL 037959 FRAME 0822. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 8, 2016
From: UNITED TEST AND ASSEMBLY CENTER LIMITED
To: UTAC HEADQUARTERS PTE. LTD.
Reel/Frame 039885/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2016
From: UNITED TEST AND ASSEMBLY CENTER LIMITED
To: UTAC HEADQUARTERS PTE. LTD.
Reel/Frame 037959/0822 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2009
From: NG, CATHERINE BEE LIANG; TOH, CHIN HOCK; SUN, ANTHONY YI SHENG
To: UNITED TEST AND ASSEMBLY CENTER, LTD
Reel/Frame 022452/0626 →