Semiconductor memory
Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AA i , AA i+1 , . . . , AA n , which extend on a memory cell array along the column length; a plurality of word line patterns WL 1 , WL 2 , . . . , extend along the row length and are non-uniformly arranged; a plurality of select gate line patterns SG 1 , SG 2 , . . . , are arranged parallel to the plurality of word line patterns; borderless contacts are formed near the ends of the word line patterns on the memory cell array, and are in contact with part of an interconnect extended from the end of the memory cell array, but are not in contact with interconnects adjacent to that interconnect; and bit line contacts are formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.
1. A semiconductor memory comprising:
a plurality of bit lines that extend on a memory cell array along the column length of the memory cell array;
a plurality of word lines that extend along the row length of the memory cell array; and
a plurality of via contacts formed at respective ends of the bit lines,
wherein, the bit lines are linearly formed, and the lengths of at least two adjacent bit lines along the column length differ from each other; and
the plurality of bit lines is arranged so that central lines of the plurality of bit lines are shorter than other lines of the plurality of bit lines and the other lines of the plurality of bit lines are successively longer along the column length, so as to be in a stepladder-shape.