IP Library Granted Patent US 7,808,308
Granted Patent B2
US 7,808,308 · App. 12/372,136 · Granted Oct 5, 2010

Voltage generating apparatus

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Quick Facts
Patent No.
US 7,808,308
App. No.
12/372,136
Granted
Oct 5, 2010
Kind
B2
Abstract

A voltage generating apparatus is disclosed. The voltage generating apparatus includes a first N-type transistor and an enhancement MOSFET transistor. The first N-type transistor has a first drain/source coupled to a first voltage, a second drain/source generating a first output voltage, and a gate coupled to a second voltage. The enhancement MOSFET transistor has a first drain/source coupled to the second drain/source of the first N-type transistor, and a second drain/source and a gate coupled to a second voltage. The first N-type transistor is a depletion metal oxide semiconductor field effect transistor (MOSFET).

Claims (27)

1. A voltage generating apparatus, comprising:

a first N-type transistor, comprising a gate, a first drain/source, and a second drain/source, the first drain/source being coupled to a first voltage, the second drain/source generating a first output voltage, and the gate being coupled to a second voltage;

an enhancement metal oxide semiconductor field effect transistor (MOSFET), comprising a gate, a first drain/source, and a second drain/source, the first drain/source being coupled to the second drain/source of the first N-type transistor, and the second drain/source and the gate being coupled to the second voltage, wherein the first N-type transistor is a depletion MOSFET; and

M second N-type transistors, connected in series in a path of coupling the first drain/source of the first N-type transistor to the first voltage, each of the second N-type transistors comprising a gate, a first drain/source, and a second drain/source, wherein M is a positive integer;

wherein the first drain/source of the 1st second N-type transistor is coupled to the first voltage, the second drain/source of the Mth second N-type transistor is coupled to the first drain/source of the first N-type transistor, and the gate of the Mth second N-type transistor is coupled to the second drain/source of the first N-type transistor, and furthermore, the second drain/source of the ith second N-type transistor is coupled to the first drain/source of the i+1th second N-type transistor, the gate of the ith second N-type transistor is coupled to the second drain/source of the i+1th second N-type transistor, 1≦i<M, and i is an integer.

2. The voltage generating apparatus according to claim 1 , the enhancement MOSFET is a P-type enhancement MOSFET, and the gate of the P-type enhancement MOSFET coupled to the second drain/source of the P-type enhancement MOSFET.

3. The voltage generating apparatus according to claim 1 , the enhancement MOSFET is a N-type enhancement MOSFET, and the gate of the N-type enhancement MOSFET coupled to the first drain/source of the N-type enhancement MOSFET.

4. The voltage generating apparatus according to claim 1 , further comprising:

a level shifting circuit, coupled to the first drain/source of the enhancement MOSFET for generating a supply voltage.

5. The voltage generating apparatus according to claim 4 , wherein the level shifting circuit is a transistor comprising a gate, a first drain/source, and a second drain/source, the gate coupled to the second drain/source of the first N-type transistor, the first drain/source of the transistor coupled to a third voltage, and the second drain/source of the transistor generates the supply voltage.

6. The voltage generating apparatus according to claim 5 , the transistor is a N-type depletion MOSFET.

7. The voltage generating apparatus according to claim 5 , further comprising:

a voltage reference circuit, coupled to the level shifting circuit and for receiving the supply voltage, the voltage reference circuit generates a reference output voltage according to the supply voltage.

8. The voltage generating apparatus according to claim 1 , wherein the second N-type transistors are depletion MOSFETs.

9. The voltage generating apparatus according to claim 1 , wherein the second drains/sources of the second N-type transistors generate M second output voltages, respectively.

10. The voltage generating apparatus according to claim 1 , further comprising:

M+1 compensation resistors, connected in series between the second drains/sources of the first and second N-type transistors and the second voltage, respectively.

11. The voltage generating apparatus according to claim 1 , further comprising:

a level shifting circuit, coupled to the second drain/source of the first N-type transistor and the second drain/source of one of the second N-type transistors, wherein the level shifting circuit receives the first output voltage and one of the second output voltages, and generates a supply voltage.

12. The voltage generating apparatus according to claim 11 , wherein the level shifting circuit is a transistor, which comprises a gate, a first drain/source, and a second drain/source, the gate is coupled to the second drain/source of the first N-type transistor, the first drain/source is coupled to the second drain/source of one of the second N-type transistors, and the second drain/source generates the supply voltage.

13. The voltage generating apparatus according to claim 12 , wherein the transistor is a depletion N-type MOSFET.

14. The voltage generating apparatus according to claim 11 , further comprising:

a voltage reference circuit, coupled to the level shifting circuit, and receiving the supply voltage, wherein the voltage reference circuit generates a reference output voltage according to the supply voltage.

15. The voltage generating apparatus according to claim 1 , further comprising:

a compensation resistor, coupled between the second drain/source of the first N-type transistor and the second voltage.

16. The voltage generating apparatus according to claim 1 , wherein the first voltage is a system voltage.

17. The voltage generating apparatus according to claim 1 , wherein the second voltage is a ground voltage.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2009
From: LAI, CHENG-HSIAO; LEE, YUAN-CHE; WU, TSUNG-CHIEN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 022271/0314 →