Method for performing plurality of bit operations and a device having plurality of bit operations capabilities
A method and a device having a plurality of bit operations capability, the device includes: a first and a second registers and an instruction fetch circuit, and an arithmetic logic unit adapted to: calculate, during a first clock cycle, a position value representative of a position, within a first information vector, of a first bit of information that has a first value; and to multiply the position value by a multiplication factor to provide a first result and to alter the value of the first bit to a second value to provide an updated information vector, during the first clock cycle.
1. A method for performing a plurality of bit operations; the method comprises:
providing an information vector;
calculating, during a first clock cycle, a position value representative of a position, within the first information vector, of a first bit of information that has a first value;
multiplying, the position value by a multiplication factor to provide a first result and altering the value of the first bit to a second value to provide an updated information vector, during the first clock cycle;
storing, during a second clock cycle, the first result at a first register; and
storing, during a third clock cycle, the updated information vector at a second register.
2. The method according to claim 1 wherein bits of the first information vector represent a validity of data within different memory entries and wherein the multiplying is followed by fetching data stored within a memory entry represented by the first bit.
3. The method according to claim 2 wherein the fetching comprises calculating an address of the memory entry represented by the first bit in response to the first result.
4. The method according to claim 1 wherein the providing is followed by decoding a find first bit, multiply and update vector instruction.
5. The method according to claim 1 wherein the first value is a high value and wherein the altering comprises resetting the first bit.
6. The method according to claim 1 wherein the providing, calculating and multiplying are repeated until the first information vector comprises only bits having the second value.
7. The method according to claim 1 wherein altering the value of the first bit comprises altering only the value of the first bit to the second value.
8. A device having a plurality of bit operations capabilities, the device comprises:
a register file including a first register and a second register, and an instruction fetch circuit;
an arithmetic logic unit adapted to:
calculate, during a first clock cycle, a position value representative of a position, within a first information vector, of a first bit of information that has a first value;
multiply, during the first clock cycle, the position value by a multiplication factor to provide a first result;
alter the value of the first bit to a second value to provide an updated information vector, during the first clock cycle;
store the first result at the first register during a second clock cycle; and
store the updated information vector at the second register during a third clock cycle.
9. The device according to claim 8 wherein bits of the first information vector represent a validity of data within different memory entries and wherein the device is adapted to fetch data stored within a memory entry represented by the first bit.
10. The device according to claim 9 wherein the arithmetic logic unit is adapted to calculate an address of the memory entry represented by the first bit in response to the first result.
11. The device according to claim 8 wherein the device comprises instruction decode circuit adapted to decode a find first bit, multiply and update vector instruction.
12. The device according to claim 8 wherein the device is adapted to calculate and multiply until the first information vector comprises only bits having a second value.
13. The device according to claim 8 wherein the arithmetic logic unit comprises a find first bit logic coupled to a bit update logic and to a multiply logic.
14. The device according to claim 13 wherein the bit update logic is coupled to the first register via two flip-flops and wherein the multiply logic is coupled via a third flip-flop to the second register.
15. The device according to claim 8 wherein in altering the value of the first bit, the arithmetic logic unit is further adapted to alter only the value of the first bit to the second value.
16. A device having a plurality of bit operations capabilities, the device comprises:
a first register, a second register, and an instruction fetch circuit; and
an arithmetic logic unit adapted to:
execute a first instruction to multiply, during a first clock cycle, a first position value by a first multiplication factor to provide a first result;
execute a second instruction to alter, during a second clock cycle, a value of a first bit from a first value to a second value; and
execute a third instruction to:
calculate, during a third clock cycle, a second position value representative of a position within an information vector of a bit of information that has the first value;
multiply, during the third clock cycle, the second position value by a second multiplication factor to provide a second result;
alter, during the third clock cycle, the value of the bit of information to the second value to provide an updated information vector
store the second result at a first register during a fourth clock cycle; and
store the updated information vector at a second register during a fifth clock cycle.
17. The device according to claim 16 wherein bits of the first information vector represent a validity of data within different memory entries and wherein the device is adapted to fetch data stored within a memory entry represented by the first bit of information.
18. The device according to claim 17 wherein the arithmetic logic unit is adapted to calculate an address of the memory entry represented by the first bit in response to the first result.
19. The device according to claim 16 wherein the device comprises instruction decode circuit adapted to decode a find first bit, multiply and update vector instruction.
20. The device according to claim 16 wherein the device is adapted to calculate and multiply until the first information vector comprises only bits having a second value.