Granted Patent B2

US 8,370,773 · App. 12/377,664 · Granted Feb 5, 2013

Abstract

Claims (30)

1. A method of designing an integrated circuit, IC, comprising the steps of:

performing inverse optical proximity correction (OPC), using a computer, to generate an optimized reticle layout design from an IC layout design and a model describing an optical system for transferring the IC layout design onto a semiconductor wafer using a reticle, wherein the optimized reticle layout design comprises features defined by a plurality of boundaries;

approximating the plurality of boundaries to generate an approximated reticle layout design suitable for the manufacture of the IC; and

performing OPC simulation on at least a portion of the approximated reticle layout design in order to identify feature defects.

2. The method of claim 1 , wherein the approximating step further comprises the step of:

identifying nodes in the plurality of boundaries.

3. The method of claim 2 , wherein the approximating step further comprises the steps of:

replacing each node with a discrete segment.

4. The method of claim 3 further comprising the step of performing OPC optimization using the approximated IC layout design.

5. The method of claim 2 , wherein the nodes are identified by applying a low-pass filter to the optimized reticle layout design.

6. The method of claim 5 further comprising the step of performing OPC optimization using the approximated IC layout design.

7. The method of claim 2 , wherein the nodes are identified by measuring the gradient along each boundary such that a specified change in gradient indicates the presence of a node.

8. The method of claim 2 further comprising the step of performing OPC optimization using the approximated IC layout design.

9. The method of claim 1 further comprising the step of flagging the identified feature defects for later investigation.

10. The method of claim 9 further comprising the step of performing OPC optimization using the approximated IC layout design.

11. The method of claim 1 further comprising the step of performing OPC optimization using the approximated IC layout design.

12. The method of claim 1 , further comprising the steps of:

identifying regions in the IC layout design having different degrees of complexity; and

performing the method steps of claim 1 on regions having a particular degree of complexity.

13. The method according to claim 12 , wherein the particular degree of complexity falls within a range of complexity.

14. The method according to claim 13 , wherein the regions having different degrees of complexity relate to memory functions and/or logic functions.

15. The method according to claim 13 , wherein the identifying step further comprises determining the feature density of the IC layout design.

16. The method according to claim 12 , wherein the regions having different degrees of complexity relate to memory functions and/or logic functions.

17. The method according to claim 16 , wherein the identifying step further comprises determining the feature density of the IC layout design.

18. The method according to claim 12 , wherein the identifying step further comprises determining the feature density of the IC layout design.

19. An apparatus for designing an integrated circuit comprising:

means for performing inverse optical proximity correction (OPC) to generate an optimized reticle layout design from an IC layout design;

a model describing an optical system for transferring the IC layout design onto a semiconductor wafer using a reticle, wherein the optimized reticle layout design comprises features defined by a plurality of boundaries;

means for approximating the plurality of boundaries to generate an approximated reticle layout design suitable for the manufacture of the IC; and

means for performing OPC simulation on at least a portion of the approximated reticle layout design.

Assignments (12)