Method for designing integrated circuit incorporating memory macro

1. An integrated circuit design method for assigning memory instances to memory macros integrated within an integrated circuit, said method comprising:

assigning a plurality of memory instances operating at a same operation frequency to a single memory macro;

arranging a frequency multiplier which receives a first clock signal to generate a second clock signal through a frequency multiplication of said first clock signal, and feeds said second clock signal to said plurality of memory instances; and

arranging a control circuit which selects said plurality of memory instances in synchronization with said first clock signal.

2. The integrated circuit design method according to claim 1 , wherein said assigning comprises providing a common address line for said plurality of memory instances, and

wherein said control circuit includes an input control circuit which selects address signals associated with said plurality of memory instances, respectively, in synchronization with said first clock signal to feed the selected address signals to said address signal line.

3. The integrated circuit design method according to claim 2 , wherein said plurality of memory instances includes a first memory instance and a second memory instance, and

wherein said assigning includes:

assigning data signal lines of upper bits of said single memory macro to said first memory instance; and

assigning data signal lines of lower bits of said single memory macro to said second memory instance.

4. The integrated circuit design method according to claim 2 , wherein said plurality of memory instances include a first memory instance and a second memory instance, and

wherein said assigning includes:

assigning word lines of an upper half of said single memory macro to said first memory instance; and

assigning word lines of an upper half of said single memory macro to said second memory instance.

5. The integrated circuit design method according to claim 1 , wherein said control circuit comprises an output control circuit reading data signals from said plurality of memory instances in synchronization with said first clock signal.

6. A tangible computer-readable recording medium which records a program that when executed controls a computer to perform a method, said method comprising:

assigning a plurality of memory instances operating at a same operation frequency to a single memory macro;

arranging a frequency multiplier which receives a first clock signal to generate a second clock signal through a frequency multiplication of said first clock signal, and feeds said second clock signal to said plurality of memory instances; and

arranging a control circuit which selects said plurality of memory instances in synchronization with said first clock signal.

7. A semiconductor integrated circuit, comprising:

a memory having a plurality of memory regions corresponding to a plurality of instances, respectively;

a frequency multiplier receiving a first clock signal to generate a second clock signal through a frequency multiplication of said first clock signal, and feeding said second clock signal to said plurality of memory instances; and

a control circuit which selects said plurality of memory instances in synchronization with said first clock signal.

8. The semiconductor integrated circuit according to claim 7 , wherein said plurality of memory regions are connected to a common address line, and

wherein said control circuit includes an input control circuit which selects address signals associated with said plurality of memory instances, respectively, in synchronization with said first clock signal to feed the selected address signals to said address signal line.

9. The semiconductor integrated circuit according to claim 8 , wherein said plurality of memory regions include first and second memory regions, and

wherein said first memory region is connected to data signal lines of upper bits of a memory macro, and

wherein said second memory region is connected to data signal lines of lower bits of said memory macro.

10. The semiconductor integrated circuit according to claim 8 , wherein said plurality of memory regions include first and second memory regions, and

wherein said first memory region incorporates word lines of an upper half of a memory macro, and

wherein said second memory region incorporates word lines of a lower half of said memory macro.

11. The semiconductor integrated circuit according to claim 7 , wherein said control circuit comprises an output control circuit reading data signals from said plurality of memory instances in synchronization with said first clock signal.

12. The semiconductor integrated circuit according to claim 7 , wherein at least one of the plurality of instances is assigned to a first memory macro, and

wherein the first memory macro performs data write, data read, and data erase operations in synchronization with the second clock signal.

13. The semiconductor integrated circuit according to claim 12 , wherein said control circuit comprises an output control circuit, and

wherein said output circuit reads data from the first memory macro in synchronization with the second clock signal and externally outputs the read data in synchronization with the first clock signal.

14. The semiconductor integrated circuit according to claim 12 , wherein the output control circuit comprises a first latch circuit configured to latch a first data signal.

15. The semiconductor integrated circuit according to claim 12 , wherein said control circuit comprises an input control circuit, the input control circuit selectively providing data signals, address signals, command signals, and chip selection signals to respective memory instances of the plurality of memory instances.