Semiconductor device manufacturing method, semiconductor device manufacturing equipment, and computer readable medium

1. A semiconductor device manufacturing method comprising:

heating a plurality of first substrates separately by a plurality of heat treatment plates, said plurality of first substrates each having on its surface a layer of first resist which is formed by exposure in a predetermined pattern;

performing a primary correction of a preset temperature for each of the plurality of heat treatment plates after said heating said plurality of first substrates;

heating a plurality of second substrates separately by said plurality of heat treatment plates at said preset temperature corrected by said primary correction, said plurality of second substrates each having a layer of second resist which is formed by exposure in said predetermined pattern on a surface of a layer of resist having the same composition as a composition of said first resist; and

performing a secondary correction of a preset temperature for each of said plurality of heat treatment plates after said heating said plurality of second substrate,

wherein said primary correction is executed based on measured dimensions of a pattern of said first resist which is obtained by developing each of said plurality of first substrates after said heating said plurality of first substrates, and

wherein said secondary correction is executed based on measured dimensions of an etching pattern which is obtained by developing and etching each of said plurality of second substrates after said heating said plurality of second substrates.

2. A semiconductor device manufacturing method comprising:

forming a layer of first resist on a principal surface of each of a plurality of first substrates;

exposing each of said plurality of first substrates to light in a predetermined pattern after said forming said layer of first resist;

heating said plurality of first substrates separately by a plurality of heat treatment plates, after said exposing each of said plurality of first substrates;

developing said each layer of first resist after said heating said plurality of first substrates;

measuring resist pattern dimensions of said each layer of first resist after developing said each layer of first resist;

performing a primary correction of a preset temperature for each of said plurality of heat treatment plates based on said measured resist pattern dimensions of said each layer of first resist;

forming a layer of second resist having the same composition as that of said first resist on a principal surface of each of a plurality of second substrates;

exposing each of said plurality of second substrates to light in the predetermined pattern after forming said layer of second resist;

heating said plurality of second substrates separately by said plurality of heat treatment plates at said preset temperature corrected by said primary correction after said exposing each of said plurality of second substrates;

developing said each layer of second resist after said heating said plurality of second substrates;

etching each of said plurality of second substrates after said developing said each layer of second resist;

measuring dimensions of an etched pattern that is formed on said principle surface of each of said plurality of second substrates after said etching each of said plurality of second substrates; and

performing a secondary correction of the preset temperature for each of said plurality of heat treatment plates based on said measured dimensions of said etched pattern.

3. The semiconductor device manufacturing method according to claim 2 ,

wherein each of said plurality of heat treatment plates have has a plurality of heating regions controlled in temperature independently of one another,

wherein said measuring dimensions of said etched pattern comprises measuring pattern dimensions in places that correspond respectively to said plurality of heating regions for each of said plurality of second substrates, and

wherein said performing said secondary correction comprises performing said secondary correction of the preset temperature for each of said plurality of heating regions of each of said plurality of heat treatment plates.

4. The semiconductor device manufacturing method according to claim 2 , further comprising:

peeling said second resist remaining on said principle surface of each of said plurality of second substrates between said etching each of said plurality of second substrates and said measuring dimensions of said etched pattern.

5. The semiconductor device manufacturing method according to claim 2 , further comprising:

checking the preset temperature corrected by said primary correction after said performing said primary correction,

wherein said checking the preset temperature corrected by said primary correction comprises:

forming a layer of third resist having the same composition as that of said first resist on a principal surface of each of a plurality of third substrates;

exposing each of said plurality of third substrates to light in said predetermined pattern after said forming the layer of said third resist;

heating said plurality of third substrates separately by said plurality of heat treatment plates at said preset temperature corrected by said primary correction after said exposing each of said plurality of third substrates;

developing each of said plurality of third substrates after said heating said plurality of third substrates separately;

measuring pattern dimensions formed on said principal surface of each of said plurality of third substrates after said developing each of said plurality of third substrates; and

re-setting said preset temperature corrected by said primary correction for each of said plurality of heat treatment plates, based on said measured pattern dimension formed on said principal surface of each of said plurality of third substrates.

6. The semiconductor device manufacturing method according to claim 2 , further comprising:

checking said preset temperature corrected by said secondary correction after said performing said secondary correction,

wherein said checking said preset temperature corrected by said secondary correction comprises:

forming a layer of fourth resist having the same composition as that of said first resist on a principal surface of each of a plurality of fourth substrates;

exposing each of said plurality of fourth substrates to light in said predetermined pattern after said forming the layer of said fourth resist;

heating said plurality of fourth substrates separately by said plurality of heat treatment plates at said preset temperature corrected by said secondary correction after said exposing each of said plurality of fourth substrates to light;

developing each layer of said fourth resist on the principal surface of each of said plurality of fourth substrates after said heating said plurality of fourth substrates separately;

etching each of said plurality of fourth substrates after said developing each layer of said fourth resist;

measuring dimensions of an etched pattern formed on the principal surface of each of said plurality of fourth substrates after said etching each of said plurality of fourth substrates; and

re-setting said preset temperature corrected by said secondary correction for each of said plurality of heat treatment plates based on said measured pattern dimension formed on the principal surface of each of said plurality of fourth substrates.

7. The semiconductor device manufacturing method according to claim 6 , further comprising:

peeling off said fourth resist remaining on the principle surface of each of said plurality of fourth substrates between said etching each of said plurality of fourth substrates and said measuring the dimensions of said etched pattern formed on the principle surface of each of said plurality of fourth substrates.

8. A computer readable medium storing a program executed by a computer for operating a semiconductor device manufacturing equipment,

wherein said semiconductor device manufacturing equipment comprises:

a plurality of heat treatment plates for performing a post-exposure bake (PEB);

a first storage section for storing a first relation, said first relation being an association relation between post-development resist pattern dimensions and a preset temperature during said PEB;

a second storage section for storing a second relation, said second relation being an association relation between post-etching pattern dimensions and the preset temperature during said PEB;

a primary correction section for obtaining post-development resist pattern dimension data for each of a plurality of first substrates processed separately by said plurality of heat treatment plates, and for primarily correcting the preset temperature for each of said plurality of heat treatment plates based on said first relation; and

a secondary correction section for obtaining post-etching pattern dimension data for each of a plurality of second substrates processed separately by said plurality of heat treatment plates at the preset temperature corrected by said primary correction, and for secondarily correcting the preset temperature for each of said plurality of heat treatment plates based on said second relation,

wherein said program comprises:

primarily correcting the preset temperature for each of said plurality of heat treatment plates based on post-development resist pattern dimension data for each of a plurality of first substrates processed separately by said plurality of heat treatment plates and said first relation stored in said first storage section; and

secondarily correcting the preset temperature for each of said plurality of heat treatment plates based on post-etching pattern dimension data for each of a plurality of second substrates processed separately by said plurality of heat treatment plates at the preset temperature corrected by said primary correction said second relation stored in said second storage section.