Semiconductor device including address signal generating protion and digital-to-analog converter

1. A semiconductor device, comprising:

a plurality of test elements formed in an array on a semiconductor substrate;

an address signal generating portion that generates an address signal corresponding to each of the test elements;

a digital-to-analog converter that receives the address signal other than through the plurality of test elements and converts the address signal into an analog signal and outputs the converted analog signal;

wherein the address signal comprises an X-coordinate address signal and a Y-coordinate address signal;

an X-coordinate switch that switches according to the X-coordinate address signal, and a Y-coordinate switch that switches according to the Y-coordinate address signal;

wherein the digital-to-analog converter comprises a resistor string type digital-to-analog converter; and

wherein a conductive type of transistors constituting the digital-to-analog converter is a same conductive type as a conductive type of transistors constituting the X-coordinate switch and the Y-coordinate switch.

2. The semiconductor device according to claim 1 , wherein the address signal comprises a plurality of address signals, and

wherein the semiconductor device further comprises a plurality of digital-to-analog converters, each of which converts a corresponding one of the plurality of address signals into an analog signal and outputs a corresponding converted analog signal.

3. The semiconductor device according to claim 1 , wherein the address signal comprises a plurality of address signals,

wherein the semiconductor device further comprises a selector that selects one of the plurality of address signals, and

wherein the semiconductor device comprises the one digital-to-analog converter that converts the selected one address signal to an analog signal and outputs the converted analog signal.

4. The semiconductor device according to claim 1 , wherein the address signal generating portion comprises a counter and a decoder.

5. The semiconductor device according to claim 4 , wherein any given address signal can be input to the decoder.

6. The semiconductor device according to claim 1 , wherein a deep N-well is formed in an area other than the area where the test element is formed, and no deep N-well is formed in the area where the test element is formed.

7. The semiconductor device according to claim 1 , wherein the digital-to-analog converter receives the address signal directly from the address signal generating portion.

8. The semiconductor device according to claim 1 , wherein the digital-to-analog converter receives the address signal from the address signal generating portion.

9. A semiconductor device, comprising:

a plurality of test elements formed in an array on a semiconductor substrate;

an address signal generating portion that generates an address signal corresponding to each of the test elements;

a digital-to-analog converter that converts the address signal into an analog signal and outputs the converted analog signal as an X-address signal and a Y-address signal;

a plurality of X-coordinate switches formed in the semiconductor substrate to designate an X-axis direction in the plurality of test elements based on the X-address signal; and

a plurality of Y-coordinate switches formed in the semiconductor substrate to designate a Y-axis direction in the plurality of test elements based on the Y-address signal,

wherein a conductive type of transistors constituting the digital-to-analog converter is a same conductive type as a conductive type of transistors constituting the plurality of X-coordinate switches and the plurality of Y-coordinate switches.

10. The semiconductor device according to claim 9 , wherein the address signal generating portion comprises:

a counter to generate a count value; and

a decoder associated with the counter to generate an X-address signal and a Y-address signal based on the count value.

11. The semiconductor device according to claim 9 , wherein the individual test elements of the plurality of test elements are arranged in an X-direction and a Y-direction on the semiconductor substrate.

12. The semiconductor device according to claim 11 , wherein a respective one of the plurality of test elements comprises a transistor.

13. The semiconductor device according to claim 9 , wherein a substrate potential of the plurality of X-coordinate switches and a substrate potential of the plurality of Y-coordinate switches arc isolated from a substrate potential of the plurality of test elements.

14. The semiconductor device according to claim 9 , further comprising a deep N-well formed in a peripheral circuit area of the plurality of test circuit,

wherein the plurality of X-coordinate switches and the plurality of Y-coordinate switches are formed in the peripheral area of the test circuit.

15. The semiconductor device according to claim 9 , further comprising a deep N-well formed below the plurality of X-switches and the plurality of Y-switches.