Input circuit and semiconductor integrated circuit including the same
View Patent ↗An input circuit, includes a first buffer circuit having an output signal terminal connected to an output; a capacitor having one end connected to an input signal terminal, and the other end connected to an input of the first buffer circuit; a first differential amplification circuit receiving a voltage of a first external power source terminal and an output of a second buffer circuit; a second differential amplification circuit receiving a voltage of a second external power source terminal and an output of a third buffer circuit; a first resistance having one end connected to an output of the first differential amplification circuit, and the other end connected between the capacitor and the first buffer circuit; and a second resistance having one end connected to an output of the second differential amplification circuit, and the other end connected between the capacitor and the first buffer circuit.
1. An input circuit, comprising:
a first buffer circuit having an output signal terminal connected to an output;
a capacitor having one end connected to an input signal terminal, and the other end connected to an input of the first buffer circuit;
a first differential amplification circuit receiving a voltage of a first external power source terminal and an output of a second buffer circuit;
a second differential amplification circuit receiving a voltage of a second external power source terminal and an output of a third buffer circuit;
a first resistance having one end connected to an output of the first differential amplification circuit, and the other end connected between the capacitor and the first buffer circuit; and
a second resistance having one end connected to an output of the second differential amplification circuit, and the other end connected between the capacitor and the first buffer circuit,
wherein:
an input of the second buffer circuit is connected to the output of the first differential amplification circuit, and
an input of the third buffer circuit is connected to the output of the second differential amplification circuit.
2. The input circuit according to claim 1 , wherein:
the first buffer circuit, the second buffer circuit, and the third buffer circuit have the same voltage gain.
3. The input circuit according to claim 2 , wherein:
the first buffer circuit, the second buffer circuit, and the third buffer circuit have the same circuit configuration.
4. The input circuit according to claim 3 , wherein:
the first buffer circuit includes a source follower circuit.
5. The input circuit according to claim 3 , wherein:
the first buffer circuit further includes:
a first MOS transistor having a gate, the gate received an input signal;
a current mirror circuit generating current mirror current corresponding to a reference current with using drain current of the first MOS transistor as the reference current; and
a second MOS transistor having a gate and a drain connected each other and received the current mirror current, and outputting a gate voltage corresponding to the current mirror current as an output voltage of the first buffer circuit.
6. The input circuit according to claim 1 , wherein:
the first buffer circuit, the second buffer circuit, and the third buffer circuit are arranged so as to be adjacent to one another.
7. The input circuit according to claim 6 , wherein:
the second buffer circuit and the third buffer circuit are arranged at symmetric positions to the first buffer circuit.