Semiconductor integrated circuit
Power wiring comprises a first-layer power wiring cluster in which VDD wiring trace and VSS wiring trace of different potentials at single trace width are arranged alternatingly; a second-layer power wiring cluster, disposed in a layer overlying the first-layer power wiring cluster, in which a VDD wiring trace and a VSS wiring trace of different potentials at single trace width are arranged alternatingly; and vias, placed in areas where the first-layer power wiring cluster and second-layer power wiring clusters intersect three-dimensionally, for electrically connecting wiring traces of the same potential in the first-layer power wiring cluster and wiring traces of the same potential in the second-layer power wiring cluster. A signal-wiring formation area is provided between mutually adjacent first-layer power wiring clusters and between mutually adjacent second-layer power wiring clusters. Design rule violation regarding via density is avoided without decline in integration or an increase in chip area.
1 . A semiconductor integrated circuit comprising:
a power wiring structure in which wiring traces of the same potential in each wiring-trace cluster are electrically connected each other by vias in areas where wiring-trace clusters intersect each other three-dimensionally, the wiring-trace clusters each having alternatingly arranged wiring traces of different potentials at a single trace width; and
a signal-wiring formation area for forming a signal wiring(s) between mutually adjacent ones of the wiring-trace clusters placed in the same layer.
2 . The semiconductor integrated circuit according to claim 1 , wherein a trace width of the wiring traces in said wiring-trace clusters is the same as that of the signal wiring(s).
3 . The semiconductor integrated circuit according to claim 1 , wherein a trace pitch of the wiring traces in said wiring-trace clusters is the same as that of the signal wirings.
4 . The semiconductor integrated circuit according to claim 1 , wherein said power wiring structure includes:
a plurality of first wiring-trace clusters in which wiring traces of different potentials at a single trace width are arranged alternatingly;
a plurality of second wiring-trace clusters, placed in a layer overlying said first wiring trace clusters, in which wiring traces of different potentials at a single trace width are arranged alternatingly; and
a plurality of vias, which are arranged in areas where said first wiring-trace clusters and said second wiring-trace clusters intersect three-dimensionally, electrically connecting wiring traces of the same potential in said first wiring-trace clusters to wiring traces in said second wiring-trace clusters;
said signal-wiring formation area being provided between mutually adjacent first wiring-trace clusters and between mutually adjacent second wiring-trace clusters.
5 . The semiconductor integrated circuit according to claim 4 , wherein
in said first wiring-trace clusters, first and second wiring traces of different potentials at a single trace width are arranged alternatingly;
in said second wiring-trace clusters, first and second wiring traces of different potentials at a single trace width are arranged alternatingly; and
said vias include:
a plurality of first vias electrically connecting the first wiring traces of said first wiring-trace clusters to the first wiring traces of said second wiring-trace clusters; and
a plurality of second vias electrically connecting the second wiring traces of said first wiring-trace clusters to the second wiring traces of said second wiring-trace clusters.