Differential amplifier circuit having offset adjustment circuit
View Patent ↗A differential amplifier circuit includes an offset adjuster circuit for varying the active load to adjust the offset caused by the differential pair. The differential amplifier circuit includes fine adjustment cell sections including a plurality of transistors having the substantially same size, and shift cell sections including transistors, whose transistor size is larger than the transistors of the fine adjustment cell sections.
1. A differential amplifier circuit including an offset adjusting circuit to adjust an offset generated by a differential pair, the offset adjusting circuit comprising:
a fine adjustment cell section including a plurality of first transistors having substantially a same transistor size; and
a shift cell section including a plurality of second transistors, each having a size greater than a size of each one of the plurality of first transistors of the fine adjustment cell section,
wherein each of the plurality of first transistors comprises a fixed resolution transistor and each of the plurality of second transistors comprises a weighted transistor.
2. The differential amplifier circuit according to claim 1 , wherein each transistor of the plurality of second transistors have different transistor sizes.
3. The differential amplifier circuit according to claim 1 , wherein the plurality of first transistors includes a transistor which comprises a smallest transistor in a semiconductor device which is provided in the differential amplifier circuit.
4. A differential amplifier circuit, comprising:
a transistor pair which constitutes a differential pair;
a first offset adjustment circuit including a plurality of first transistors being substantially identical including with respect to a substantially same size, in order to adjust an offset produced by the transistor pair; and
a second offset adjustment circuit including a plurality of second transistors which have a transistor size greater than the size of the first transistors, in order to adjust the offset produced by the transistor pair.
5. The differential amplifier circuit of claim 1 , wherein each transistor of the plurality of first transistors has substantially a same adjustment resolution.
6. The differential amplifier circuit of claim 1 , wherein each transistor of the plurality of first transistors has substantially a same variation in adjustment resolution.
7. The differential amplifier circuit of claim 1 , wherein the fine adjustment cell section is provided for each side of the differential pair.
8. The differential amplifier circuit of claim 1 , wherein the shift cell section is coupled to each side of the differential pair.
9. The differential amplifier circuit of claim 1 , wherein the shift cell section and the fine adjustment cell section are both in parallel with the transistors of the differential pair, and
wherein each of the first transistors are grouped in the fine adjustment cell section separate from a grouping of the second transistors in the shift cell section.
10. The differential amplifier circuit of claim 1 , further comprising a switch coupled to each of the first transistors and each of the second transistors to selectively adjust the offset generated by the differential pair.
11. The differential amplifier circuit of claim 4 , wherein each transistor of the plurality of first transistors has substantially a same adjustment resolution.
12. The differential amplifier circuit of claim 4 , wherein each transistor of the plurality of first transistors has substantially a same variation in adjustment resolution.
13. The differential amplifier circuit of claim 4 , wherein the first offset adjustment circuit is coupled to each transistor of the transistor pair.
14. The differential amplifier circuit of claim 4 , wherein the second offset adjustment circuit is provided on each side of the transistor pair.
15. The differential amplifier circuit of claim 4 , wherein the first and second offset adjustment circuits are in parallel with the transistor pair.
16. The differential amplifier circuit of claim 4 , further comprising a switch coupled to each of the first transistors and each of the second transistors, to selectively adjust the offset generated by the transistor pair.
17. An offset adjusting circuit for a differential amplifier circuit including an offset adjusting circuit to adjust an offset generated by a differential pair, the offset adjusting circuit comprising:
a fine adjustment cell section on each side of the differential pair, each of the fine adjustment cell sections including a plurality of first transistors having substantially a same transistor size and substantially a same adjustment resolution; and
a shift cell section on each side of the differential pair, each of the shift cell sections including a plurality of second transistors, each of the plurality of second transistors having a size greater than a size of each one of the plurality of first transistors of the fine adjustment cell section,
wherein each transistor of the plurality of first transistors is a fixed resolution transistor and each transistor of the plurality of second transistors is a weighted transistor, and
wherein the first transistors have less variation of adjustment resolution than the second transistors.
18. The offset adjusting circuit of claim 17 , wherein each of the shift cell sections and the fine adjustment cell sections are in parallel with a corresponding transistor of the differential pair.
19. The offset adjusting circuit of claim 17 , further comprising a switch coupled to each of the first transistors and each of the second transistors to selectively adjust the offset generated by the differential pair.
20. The offset adjusting circuit of claim 17 , wherein each one of the first transistors is substantially identical.