Position aligning apparatus, position aligning method, and semiconductor device manufacturing method
View Patent ↗A position aligning apparatus performs position alignment of a pattern in a current process of a pattern exposure process by using a pattern formed before the current process. The position aligning apparatus includes: a correction calculating section configured to calculate a correction value set of a current lot about each of misalignments in scale and rotation of a pattern in a chip in the current process based on a correction value set in an immediately-preceding lot in the current process, a completeness value set in the immediately-preceding lot in the current process, a summation of completeness value sets in the immediately-preceding lot to a process immediately-preceding to the current process, and a summation of completeness value sets in the current lot to the immediately-preceding process; and a correction control unit configured to control correction of the scale and the rotation of the pattern in the chip by using the correction value sets.
1. A method of manufacturing a semiconductor device, said method comprising:
position aligning a pattern of a semiconductor wafer in a current process of a pattern exposure process using information on a pattern that is formed before the current process; and
exposing the semiconductor wafer,
wherein said position aligning comprises:
calculating a correction value set of a current lot for each of misalignments in a scale and a rotation of the pattern in a chip in the current process based on a correction value set in an immediately-preceding lot in the current process, a completeness value set in the immediately-preceding lot in the current process, a summation of completeness value sets for preceding processes to the current process in the immediately-preceding lot, and a summation of completeness value sets for preceding processes to the current process in the current lot; and
controlling a correction of a shift, the scale, and the rotation of the pattern in the chip by using the correction value sets.
2. The method according to claim 1 , further comprising:
calculating other correction value sets of misalignments in the scale and the rotation in the current process based on a correction value set in the immediately-preceding lot in the current process, the completeness value set in the immediately-preceding lot in the current process, a summation of completeness value sets for preceding processes to the current process in the immediately-preceding lot, and a summation of completeness value sets completeness value sets for preceding processes to the current process in the current lot; and
controlling the correction of the scale and the rotation of the pattern in the chip by using the other correction value sets.
3. The method according to claim 1 , further comprising:
relating the correction value set and the completeness value set in each of processes of the exposure process to an exposure unit for the exposure process and a lot number of the exposure process to store in a database.
4. The method according to claim 1 , wherein the position alignment of the pattern in the current process is performed by using a pattern formed in the immediately-preceding process.
5. The claim according to claim 1 , further comprising:
calculating other correction value sets of misalignments in the shift, the scale, and the rotation in the current process based on a correction value set in the immediately-preceding lot in the current process, and the completeness value set in the immediately-preceding lot in the current process; and
controlling the correction of the scale and the rotation of the pattern in the chip by using the other correction value sets.
6. The method according to claim 1 , wherein an exposure correction value set Cij of a j th exposure process in a current i th lot is calculated based on
Cij=C ( i− 1) j+M ( i− 1) j −( M ( i− 1)1+. . . + M ( i− 1)( j− 1))+( Mi 1 +. . . +Mi ( j− 1))
where the current lot is an i th lot, the immediately-preceding lot is an (i−1) th lot, the current process is a j th exposure process, C(i−1)j is an exposure correction value set of a j th exposure process in an immediately-preceding (i−1) th lot, M(i−1)j is a completeness value set of the j th exposure process in the immediately-preceding (i−1) th lot, M(i−1)1+. . . +M(i−1)(j−1) is a summation of completeness value sets of a 1 st to (j−1) th exposure processes in an immediately-preceding (i−1) th lot, and Mi1+. . . +Mi (j−1) is a summation of the completeness value sets of the 1 st to (j−1) th exposure processes in the current i th lot.
7. A method of manufacturing a semiconductor device, said method comprising:
position aligning a pattern of a semiconductor wafer in a current process of a pattern exposure process using a information on a pattern that is formed before an immediately-preceding process to the current process; and
exposing the semiconductor wafer,
wherein said position aligning comprises:
calculating a correction value set of a current lot for each of misalignments in a shift, a scale, and a rotation of the pattern in a chip in the current process based on a correction value set in an immediately-preceding lot in the current process, a completeness value set in the immediately-preceding lot in the current process, a completeness value set in the immediately-preceding lot in the immediately-preceding process, and a completeness value set in the current lot to the immediately-preceding process; and
controlling a correction of the shift, the scale, and the rotation of the pattern in the chip by using the correction value sets.
8. The method according to claim 7 , further comprising:
calculating other correction value sets of misalignments in the scale and the rotation in the current process based on a correction value set in the immediately-preceding lot in the current process, the completeness value set in the immediately-preceding lot in the current process, a summation of completeness value sets for preceding processes to the current process in the immediately-preceding lot, and a summation of completeness value sets completeness value sets for preceding processes to the current process in the current lot; and
controlling the correction of the scale and the rotation of the pattern in the chip by using the other correction value sets.
9. The method according to claim 7 , further comprising:
relating the correction value set and the completeness value set in each of processes of the exposure process to an exposure unit for the exposure process and a lot number of the exposure process to store in a database.
10. The method according to claim 7 , wherein the position alignment of the pattern in the current process is performed by using a pattern formed in the immediately-preceding process.
11. The claim according to claim 7 , further comprising:
calculating other correction value sets of misalignments in the shift, the scale, and the rotation in the current process based on a correction value set in the immediately-preceding lot in the current process, and the completeness value set in the immediately-preceding lot in the current process; and
controlling the correction of the scale and the rotation of the pattern in the chip by using the other correction value sets.
12. The method according to claim 7 , wherein an exposure correction value set Cij of a j th exposure process in a current i th lot is calculated based on
Cij=C ( i− 1) j+M ( i− 1) j−M ( i− 1)( j− 1)+ Mi ( j− 1)
where the current lot is an i th lot, the immediately-preceding lot is an (i−1) th lot, the current process is the j th exposure process, C(i−1)j is an exposure correction value of the j th exposure process in an immediately-preceding (i−1) th lot, M(i−1)j is the completeness value set of the j th exposure process in the immediately-preceding (i−1) th lot, M(i−1)(j−1) is the completeness value set of a (j−1) th exposure process in the immediately-preceding (i−1) th lot, and Mi(j−1) is the completeness value set of the (j−1) th exposure process in the current i th lot.