Semiconductor device
In order to solve a problem in a conventional semiconductor device that improvement of resistance to electrostatic discharge damage or improvement of an area efficiency is severely restricted, there is provided a semiconductor device including: a first protection diode (DP) having an anode which is connected to a signal wire connected to an I/O pad (PAD), and having a cathode which is connected to a power supply wire (VDD); a power clamp circuit ( 10 ) connected between the power supply wire (VDD) and a ground wire (GND); a slot in which a set of the I/O pad (PAD) and the first protection diode (DP) is formed; and a power clamp circuit formation region in which the power clamp circuit ( 10 ) is formed, in which the power clamp circuit formation region has a side adjacent to a plurality of the slots, and has a width (W 2 ) larger than a width of the slot.
1 . A semiconductor device, comprising:
a first protection diode having an anode which is connected to a signal wire connected to an input/output pad, and having a cathode which is connected to a power supply wire;
a power clamp circuit connected between the power supply wire and a ground wire;
a slot in which a set of the input/output pad and the first protection diode is formed; and
a power clamp circuit formation region in which the power clamp circuit is formed,
wherein the power clamp circuit formation region has a side adjacent to a plurality of the slots, and has a width larger than a width of the slot.
2 . A semiconductor device according to claim 1 , wherein the first protection diode is arranged in a position closest to the power clamp circuit formation region in the slot.
3 . A semiconductor device according to claim 1 , wherein the first protection diode is adjacent to another first protection diode provided in an adjacent slot of the plurality of the slots through a device isolation region.
4 . A semiconductor device according to claim 1 , wherein:
the power clamp circuit comprises a power clamp transistor formed in a region surrounded by a guard ring region; and
the guard ring region has a width larger than the width of the slot.
5 . A semiconductor device according to claim 4 , further comprising a trigger circuit for controlling the power clamp transistor to be a conductive state when abnormality due to static electricity occurs in the input/output pad.
6 . A semiconductor device according to claim 4 , wherein the power clamp transistor has a control terminal connected to the ground wire.
7 . A semiconductor device according to claim 4 , wherein the power clamp transistor includes a MOS transistor.
8 . A semiconductor device according to claim 1 , further comprising a second protection diode formed in the slot and connected between the signal wire and the ground wire.