Substrate bias circuit and method for integrated circuit device
View Patent ↗A substrate biasing circuit may include a first pump control circuit that generates a first control signal in response to a first reference voltage and a voltage of a first substrate portion, and includes a first reference generator coupled between a temperature compensated voltage and a reference power supply voltage that varies the first reference voltage in response to the voltage of the first substrate voltage and the temperature compensated voltage. A first clamp circuit may generate a first clamp signal in response to a first limit voltage and the voltage of the first substrate portion, the first limit voltage being a scaled version of the temperature compensated voltage. A first charge pump may pump the first substrate portion in at least a first voltage direction in response to the first control signal, and is prevented from pumping in the first voltage direction in response to the first clamp signal.
1. A substrate biasing circuit, comprising:
a first pump control circuit that generates a first control signal in response to a first reference voltage and a voltage of a first substrate portion, and includes a first reference generator coupled between a temperature compensated voltage and a reference power supply voltage that varies the first reference voltage in response to the voltage of the first substrate portion and the temperature compensated voltage;
a first clamp circuit that generates a first clamp signal in response to a first limit voltage and the voltage of the first substrate portion, the first limit voltage being a scaled version of the temperature compensated voltage; and
a first charge pump that pumps the first substrate portion in at least a first voltage direction in response to the first control signal, and is at least prevented from pumping in the first voltage direction in response to the first clamp signal.
2. The substrate biasing circuit of claim 1 , wherein:
the first reference generator includes a first bias transistor having a body coupled to receive the voltage of the first substrate portion.
3. The substrate biasing circuit of claim 2 , wherein:
the first reference generator further includes a first reference impedance coupled in series with the source-drain path of the first bias transistor between the temperature compensated voltage and the reference supply voltage.
4. The substrate biasing circuit of claim 1 , wherein:
the first pump control circuit includes a first reference amplifier having a first input coupled to receive the first reference voltage and a second input coupled to the voltage of the first substrate portion; and
the first clamp circuit includes a first clamp amplifier having a first input coupled to receive the first limit voltage and a second input coupled to the voltage of the first substrate portion.
5. The substrate biasing circuit of claim 1 , wherein:
the first substrate portion is of p-type conductivity; and
the first pump control circuit further includes a polarity inversion circuit that changes the polarity of the voltage of the first substrate portion before applying it to the first reference amplifier.
6. The substrate biasing of circuit 1 , further including:
a band gap reference voltage circuit that generates the temperature compensated reference voltage.
7. The substrate biasing circuit of claim 1 , further including:
a second pump control circuit that generates a second control signal in response to the first reference voltage and a voltage of a second substrate portion of a different conductivity type than the first substrate portion, the second pump control circuit including a second reference generator coupled between the temperature compensated voltage and the reference power supply voltage that varies the second reference voltage in response to the voltage of the second substrate portion and the temperature compensated voltage.
8. A substrate bias circuit, comprising:
a first clamp circuit that activates a first clamp signal in response to a comparison between a first limit voltage and a first substrate voltage;
a first control circuit that activates a first pump signal in response to a comparison between a first reference voltage and the first substrate voltage;
a second clamp circuit that activates a second clamp signal in response to a comparison between a second limit voltage and a second substrate voltage;
a first charge pump that is prevented from pumping a first substrate portion in a first voltage direction in response to the first clamp signal, the first charge pump pumping the first substrate portion in the first voltage direction in response to the first pump signal unless overridden by the first clamp signal; and
a second charge pump that is prevented from pumping a second substrate portion in a second voltage direction in response to the second clamp signal; wherein
the first and second limit voltages are generated from a temperature compensated voltage.
9. The substrate bias circuit of claim 8 , wherein:
the first clamp circuit includes
a first clamp amplifier having a first input coupled to receive the first limit voltage, and
a feedback polarity inversion circuit that inverts a polarity of the first substrate voltage before applying it to a second input of the first clamp amplifier.
10. The substrate bias circuit of claim 8 , wherein:
the second clamp circuit includes
a second clamp amplifier having a first input coupled to receive the second limit voltage, and
a feedback voltage scaling circuit that scales the second substrate voltage before applying it to a second input of the second clamp amplifier.
11. The substrate bias circuit of claim 8 , wherein:
the first clamp circuit includes
a first reference scaling circuit that scales a primary temperature compensated voltage to generate the first limit voltage, and
a first clamp amplifier having a first input that receives the first limit voltage and a second input coupled to the first substrate voltage; and
the second clamp circuit includes
a second reference scaling circuit that scales the primary temperature compensated voltage to generate the second limit voltage, and
a second clamp amplifier having a first input that receives the second limit voltage and a second input coupled to the second substrate voltage.
12. The substrate bias circuit of claim 8 , wherein:
the first control circuit includes a first reference generator circuit having
a reference transistor that draws a reference current and has a body comprising the first substrate portion, and
a reference impedance through which the reference current flows to generate a substrate feedback voltage for comparison with the first reference voltage.
13. A method of biasing an integrated circuit substrate, comprising:
generating a first reference voltage from a primary temperature compensated voltage;
generating a first feedback voltage in response to at least the primary temperature compensated voltage and a first substrate portion voltage;
generating a first limit voltage from the primary temperature compensated voltage; and
controlling the first substrate portion voltage in response to the first reference voltage, first feedback voltage and first limit voltage, including preventing a pumping of the first substrate portion in a first voltage direction in response to a comparison between the first limit voltage and the first substrate portion voltage.
14. The method of claim 13 , wherein:
controlling the first substrate portion voltage includes
pumping the first substrate portion in the first voltage direction in response to a comparison between the first reference voltage and the first feedback voltage.
15. The method of claim 14 , further including:
preventing the pumping of the first substrate portion includes
inverting a polarity of the first substrate portion voltage to generate a modified first substrate voltage, and
comparing the modified first substrate voltage to a scaled version of the primary temperature compensated voltage.
16. The method of claim 13 , wherein:
generating the first feedback voltage includes
coupling a body of at least one feedback transistor to the first substrate portion voltage to generate a leakage current, and
passing the leakage current through a reference impedance to generate the first feedback voltage.
17. The method of claim 13 , further including:
generating a second reference voltage from the primary temperature compensated voltage;
generating a second feedback voltage in response to at least the primary temperature compensated voltage and a second substrate portion voltage;
generating a second limit voltage from the primary temperature compensated voltage; and
controlling the second substrate portion voltage in response to the second reference voltage, second feedback voltage and second limit voltage.
18. A method of biasing an integrated circuit substrate, comprising:
generating a first reference voltage from a primary temperature compensated voltage for controlling activation of a first charge pump that controls a potential of a first substrate portion by at least pumping the first substrate portion in first and second voltage directions;
generating a first limit voltage from the primary temperature compensated voltage for limiting the potential of the first substrate portion;
generating a second reference voltage from the primary temperature compensated voltage for controlling activation of a second charge pump that controls a potential of a second substrate portion; and
generating a second limit voltage from the primary temperature compensated voltage for limiting the potential of the second substrate portion.
19. The method of claim 18 , wherein:
controlling activation of the first charge pump includes
activating the first charge pump to drive the first substrate portion in a negative voltage direction, the first substrate portion comprising a plurality of p-doped regions, each including at least one n-channel insulated gate field effect transistor; and
controlling activation of the second charge pump includes
activating the second charge pump to drive the second substrate portion in a positive voltage direction, the second substrate portion comprising a plurality of n-doped regions, each including at least one p-channel insulated gate field effect transistor.
20. The method of claim 18 , wherein:
limiting the potential of the first substrate portion includes
preventing the first charge pump from driving the first substrate portion to a voltage lower than a first predetermined voltage, the first substrate portion comprising a plurality of p-doped regions, each including at least one n-channel insulated gate field effect transistor; and
limiting the potential of the second substrate portion includes
preventing the second charge pump from driving the second substrate portion to a voltage higher than a second predetermined voltage, the second substrate portion comprising a plurality of n-doped regions, each including at least one p-channel insulated gate field effect transistor.
21. The method of claim 18 , wherein:
generating the first reference voltage includes biasing a first reference transistor between the primary temperature compensated voltage and a reference supply voltage, a body of the first reference transistor being formed in the first substrate portion; and
generating the second reference voltage includes biasing a second reference transistor between the primary temperature compensated voltage and the reference supply voltage, a body of the second reference transistor being formed in the second substrate portion.
22. The method of claim 18 , wherein:
controlling activation of the first charge pump includes comparing the first reference voltage to the voltage of the first substrate portion and pumping the first substrate portion in the first voltage direction in response to a first compare result, and pumping the first substrate portion in the second voltage direction in response to a second compare result.