Charge pump circuit and method

1 . A stage of a charge pump circuit comprising:

a first and a second node for alternately being charged and discharged, each node having an n-channel input device and a p-channel output device; and

a boosting circuit for alternately boosting a potential on the one of the first and second nodes being discharged;

wherein (a) each n-channel device is formed in a p-well disposed in an n-well, and comprises a common source region and a pair of drain regions on opposite sides of the source region defining a pair of channel regions, (b) a pair of gates is disposed above the channel region, the gates being coupled to the boosting circuit, (c) the source regions is coupled to one of the nodes, and (d) the drain regions, n-well, and p-well are coupled to one of the input devices.

2 . The stage of claim 1 , wherein the boosting circuit comprises first and second capacitors coupled to the first and second nodes, respectively, the capacitors receiving complementary clock signals.

3 . The stage of claim 2 , wherein the boosting circuit pulls down the node being charged.

4 . The stage of claim 3 , wherein the boosting circuit comprises a clock circuit providing the complementary clock signals.

5 . (canceled)

6 . (canceled)

7 . A charge pump circuit including a first stage and a second stage each comprising the stages of claim 1 , and

wherein the first node of the second stage is coupled to receive charge from the first node of the first stage, and wherein charge from the first node of the first stage is discharge while the first node of the second stage is charged.

8 . A stage for a charge pump circuit comprising:

first and second n-channel input devices coupled to first and second circuit legs, respectively;

first and second p-channel output devices coupled to outputs of the first and second circuit legs, respectively, with a first node for storing charge disposed between the first input device and first output device, and a second node for storing charge disposed between the second input device and second output device; and

a clock circuit for turning on the first input device and second output device while turning off the second input device and first output device during a first period of time, and then, for turning on the second input device and first output device while turning off the first input device and second output device during a second period of time, the clock circuit boosting a potential on the first node during the second period of time, and boosting a potential on the second node during the first period of time;

wherein (a) each n-channel device is formed in a p-well disposed in an n-well, and comprises a common source region and a pair of drain regions on opposite sides of the source region defining a pair of channel regions, (b) a pair of gates are disposed above the channel region, the gates being coupled to the clock circuit through a capacitor, (c) the source regions is coupled to one of the nodes, and (d) the drain regions, n-well, and p-well are coupled to one of the input devices.

9 . (canceled)

10 . (canceled)

11 . The stage of claim 8 , wherein the p-channel devices are in a common n-well along with two other p-channel devices which alternately couple the n-well to the first and second nodes.

12 .- 20 . (canceled)

21 . A stage in a charge pump circuit having an input device and an output device where the input device comprises:

an n-channel device formed in a p-well disposed in an n-well, a source region with drain regions disposed on opposite sides defining a pair of channel regions therebetween, a gate disposed above each channel region, where the source region is coupled to a node in the stage charged from a stage input and where the drain regions, n-well and p-wells are coupled to the stage input.

22 . The stage of claim 21 , wherein each stage includes a p-channel device coupled between the node and a stage output.