Patent Assignment
Reel/Frame 027126/0176
Assignment of Assignor's Interest
Recorded: 2011-10-26
Pages: 28
Assignor
NUMONYX B.V.
Executed: 2011-09-30
Assignee
MICRON TECHNOLOGY, INC.
8000 S. FEDERAL WAY, BOISE, IDAHO, 83707
Covered Properties
(214)
Peak Reduction for Simulcast Broadcast Signals
Low Temperature Board Level Assembly Using Anisotropically Conductive Materials
Application:
12/271,077 →
Publication:
US 2010/0123258
Password Protected Built-in Test Mode for Memories
Increasing the Spatial Resolution of Dosimetry Sensors
Non-Volatile Memory Device Capable of Initiating Transactions
Multilevel Encoding with Error Correction
Reading Threshold Switching Memory Cells
Package on Package Assembly using Electrically Conductive Adhesive Material
Application:
12/334,517 →
Publication:
US 2010/0148359
Reduced Signal Interface Memory Device, System, and Method
Providing a Ready-Busy Signal from a Non-Volatile Memory Device to a Memory Controller
Memory with Guard Value Dependent Error Correction
Method and Apparatus for Configuring Write Performance for Electrically Writable Memory Devices
Patent:
8,725,928 →
Application:
12/337,573 →
Wordline Temperature Compensation
Shallow Trench Isolation for a Memory
Integrating Diverse Transistors on the Same Wafer
Fabricating Bipolar Junction Select Transistors for Semiconductor Memories
Forming Isolation Regions for Integrated Circuits
Configurable Latching for Asynchronous Memories
Molding Compound Including a Carbon Nano-Tube Dispersion
Nonvolatile/Volatile Memory Write System and Method
Application:
12/343,485 →
Publication:
US 2010/0162038
Rewritable Single-Bit-Per-Cell Flash Memory
Patent:
7,978,529 →
Application:
12/344,157 →
Controlling the Circuitry and Memory Array Relative Height in a Phase Change Memory Feol Process Flow
Method and Apparatus to Profile Ram Memory Objects for Displacment with Nonvolatile Memory
Application:
12/345,306 →
Publication:
US 2010/0169708
Method for Low-Stress Multilevel Reading of Phase Change Memory Cells and Multilevel Phase Change Memory
Method for Low Power Accessing a Phase Change Memory Device
An Apparatus Including a Follower Output Buffer Having an Output Impedance That Adapts to a Transmission Line Impedance
Apparatus and Method for Refreshing or Toggling a Phase-Change Memory Cell
Patent:
7,986,549 →
Application:
12/345,462 →
Erase Completion Recognition
Lithographic Patterning for Sub-90NM with a Multi-Layered Carbon-Based Hardmask
Patent:
7,803,715 →
Application:
12/345,568 →
Protective Thin Film Coating in Chip Packaging
Application:
12/345,572 →
Publication:
US 2010/0164083
Secondary Memory Element for Non-Volatile Memory
Patent:
8,458,562 →
Application:
12/346,015 →
Method of Fabricating a Charge Trap Nand Flash Memory Device
Patent:
8,329,545 →
Application:
12/346,363 →
Dynamic Polarization for Reducing Stress Induced Leakage Current
Patent:
7,940,568 →
Application:
12/346,472 →
Enhanced Throughput for Serial Flash Memory, Including Streaming Mode Operations
Patent:
8,250,287 →
Application:
12/347,510 →
Extended Address Mode for Serial Flash Memory
Patent:
8,380,914 →
Application:
12/347,623 →
Method of High Aspect Ratio Plug Fill
Multi-Die Building Block for Stacked-Die Package
Method for Patterning a Photo-Resist in an Immersion Lithography Process
Patent:
7,704,674 →
Application:
12/347,786 →
Semiconductor Package Substrate with Metal Bumps
Application:
12/347,800 →
Publication:
US 2010/0167466
Writing to Non-Volatile Memory During a Volatile Memory Refresh Cycle
Patent:
7,944,764 →
Application:
12/347,900 →
Recovery for Non-Volatile Memory After Power Loss
Method and Apparatus for an Always Open Write-Only Register Based Memory Mapped Overlay Interface for a Nonvolatile Memory
Patent:
8,327,087 →
Application:
12/347,962 →
Method and Apparatus for Active Range Mapping for a Nonvolatile Memory Device
Application:
12/347,983 →
High Impedance Reference Voltage Distribution
Patent:
7,903,478 →
Application:
12/355,466 →
Erase Verification for Flash Memory
Patent:
8,014,208 →
Application:
12/357,940 →
Charge pump circuit and method
Application:
12/387,655 →
Publication:
US 2010/0283533
Forming Low Dielectric Constant Dielectric Materials
Patent:
7,935,627 →
Application:
12/398,298 →
Filling Gaps in Integrated Circuit Fabrication
Application:
12/411,450 →
Publication:
US 2010/0244181
Password Accessible Microelectronic Memory
Enabling A Secure Boot From Non-Volatile Memory
Patent:
9,058,491 →
Application:
12/411,784 →
Control Signal Output Pin to Indicate Memory Interface Control Flow
Application:
12/412,829 →
Publication:
US 2010/0250828
Memory Devices Having Data Flow Pipelining
Patent:
8,516,181 →
Application:
12/415,973 →
Hierarchical Memory Architecture to Connect Mass Storage Devices
Hierarchical Memory Architecture Using a Concentrator Device
Hierarchical Memory Architecture with an Interface to Differing Memory Formats
Application:
12/416,008 →
Publication:
US 2010/0250798
Hierarchical Memory Architecture with a Phase-Change Memory (Pcm) Content Addressable Memory (Cam)
High Rate Selective Polymer Growth on a Substrate
Method for Writing to and Erasing a Non-Volatile Memory
Non-Volatile Memory with Extended Error Correction Protection
Method and Apparatus for Efficient Memory Placement
Application:
12/433,763 →
Publication:
US 2010/0169602
Method and Apparatuses for Managing Double Data Rate in Non-Volatile Memory
Patent:
7,995,365 →
Application:
12/434,600 →
Method and Apparatus for Preventing Foreground Erase Operations in Electrically Writable Memory Devices
Patent:
8,225,042 →
Application:
12/435,986 →
Signal Shifting to Allow Independent Control of Identical Stacked Memory Modules
Patent:
8,198,717 →
Application:
12/463,329 →
Using Out-of-Band Signaling to Communicate with Daisy Chained Nonvolatile Memories
Application:
12/463,337 →
Phase-Change Memory Temperature Sensitive Detector
Patent:
8,259,488 →
Application:
12/464,011 →
Dedicated Interface to Factory Program Phase-Change Memories
Wireless Interface to Program Phase-Change Memories
Pcm Memories for Storage Bus Interfaces
Non-Volatile Memory with Bi-Directional Error Correction Protection
Method and Devices for Controlling Power Loss
Configurable Partitions for Non-Volatile Memory
Patent:
8,230,196 →
Application:
12/473,629 →
Method for Operating a Portion of an Executable Program in an Executable Non-Volatile Memory
Application:
12/477,017 →
Publication:
US 2010/0306453
Phase Change Memory Cell with Self-Aligned Vertical Heater
Application:
12/481,496 →
Publication:
US 2010/0308296
Error Correcting Codes for Increased Storage Capacity in Multilevel Memory Devices
Memory Device for a Hierarchical Memory Architecture
Limiting Flash Memory Over Programming
Patent:
8,755,229 →
Application:
12/490,002 →
Pinning Content in Nonvolatile Memory
Memory with Sub-Blocks
Patent:
8,130,550 →
Application:
12/491,160 →
Hardwired Remapped Memory
Patent:
8,412,985 →
Application:
12/494,830 →
Bit Error Threshold and Remapping a Memory Device
Application:
12/494,904 →
Publication:
US 2010/0332894
Bit Error Threshold and Content Addressable Memory to Address a Remapped Memory Device
Application:
12/494,950 →
Publication:
US 2010/0332950
Non-Volatile Memory to Store Memory Remap Information
Externally Maintained Remap Information
Patent:
8,161,334 →
Application:
12/495,032 →
Switchable on-Die Memory Error Correcting Engine
Patent:
8,495,467 →
Application:
12/495,081 →
Phase Change Memory Cell with Self-Aligned Vertical Heater and Low Resistivity Interface
Phase Change Memory in a Dual Inline Memory Module
Non-Volatile Memory
Patent:
8,211,762 →
Application:
12/512,907 →
Non-Volatile Memory with Extended Operating Temperature Range
Selective Refresh of Single Bit Memory Cells
Patent:
7,936,610 →
Application:
12/534,792 →
Daisy Chaining Nonvolatile Memories
Patent:
8,700,845 →
Application:
12/539,771 →
High-Speed Wireless Serial Communication Link for a Stacked Device Configuration Using Near Field Coupling
Full Chip Wear Leveling in Memory Device
Patent:
8,601,202 →
Application:
12/548,375 →
Maintenance Process to Enhance Memory Endurance
Dual Mode Clock and Data Scheme for Memory Programming
Patent:
8,804,411 →
Application:
12/557,723 →
Autonomous Memory Architecture
Autonomous Memory Subsystem Architecture
Partitioning Process to Improve Memory Cell Retention
Integrated Circuit Edge and Method to Fabricate the Same
Patent:
8,093,090 →
Application:
12/577,602 →
Non-Volatile Sram Cell That Incorporates Phase-Change Memory into a Cmos Process
Block-Based Storage Device with a Memory-Mapped Interface
Patent:
8,898,417 →
Application:
12/582,643 →
Error-Correcting Code and Process for Fast Read-Error Correction
Patent:
8,332,731 →
Application:
12/612,935 →
Method and Apparatuses for Customizable Error Correction of Memory
Word-Line Driver Including Pull-Up Resistor and Pull-Down Transistor
Reliable Set Operation for Phase-Change Memory Cell
Error Correction Code for Unidirectional Memory
Write Performance of Phase Change Memory Using Set-Pulse Shaping
Patent:
8,199,566 →
Application:
12/623,926 →
Authenticated Operations and Event Counters
Patent:
8,566,940 →
Application:
12/625,716 →
Self-Aligned Cross-Point Phase Change Memory-Switch Array
Application:
12/627,080 →
Chemical-Mechanical Polish Termination Layer to Build Electrical Device Isolation
Patent:
8,093,576 →
Application:
12/627,128 →
Memory to Store User-Configurable Data Polarity
Patent:
8,085,584 →
Application:
12/627,214 →
Stored Multi-Bit Data Characterized by Multiple-Dimensional Memory States
Keyhole-Free Sloped Heater for Phase Change Memory
Package Including an Underfill Material in a Portion of an Area Between the Package and a Substrate or Another Package
Package Including an Interposer Having at Least One Topological Feature
Package Including at Least One Topological Feature on an Encapsulant Material to Resist Out-of-Plane Deformation
System, Apparatus, and Reading Method for Nand Memories
Patent:
8,248,851 →
Application:
12/628,073 →
Multi-Partitioning Feature on E-Mmc
Patent:
8,307,151 →
Application:
12/628,152 →
Phase Change Memory Device with Reduced Programming Disturbance
Patent:
8,243,497 →
Application:
12/628,153 →
Dynamic Range Unlock or Lock Memory Device and Method to Operate the Same
Patent:
8,392,683 →
Application:
12/628,166 →
Wireless Communication Link Using Near Field Coupling
Patent:
9,401,745 →
Application:
12/635,961 →
Persistent Content in Nonvolatile Memory
Nonvolatile Memory Internal Signature Generation
Flash Translation Layer Using Phase Change Memory
Application:
12/638,956 →
Publication:
US 2011/0145477
Serial Parallel Interface for Data Word Architecture
Patent:
8,117,351 →
Application:
12/647,879 →
Multi-Channel Memory and Power Supply-Driven Channel Selection
Patent:
8,254,199 →
Application:
12/648,762 →
Via Formation for Cross-Point Memory
Patent:
8,431,446 →
Application:
12/648,979 →
Self-Adaptive Solid State Drive Controller
Patent:
9,442,866 →
Application:
12/649,954 →
Solid State Drive Controller
Patent:
9,612,775 →
Application:
12/650,035 →
Sub-Os Virtual Memory Management Layer
Self-Selecting Pcm Device Not Requiring a Dedicated Selector Transistor
Supply Voltage or Ground Connections for Integrated Circuit Device
Patent:
8,536,716 →
Application:
12/651,122 →
Nonvolatile Storage with Disparate Memory Types
Application:
12/652,666 →
Publication:
US 2011/0167197
Apparatuses and Methods for Sensing a Phase-Change Test Cell and Determining Changes to the Test Cell Resistance Due to Thermal Exposure
Patent:
8,351,289 →
Application:
12/655,377 →
Forming Array Contacts in Semiconductor Memories
Patent:
8,569,891 →
Application:
12/724,491 →
Supply Voltage or Ground Connections Including Bond Pad Interconnects for Integrated Circuit Device
Patent:
8,531,849 →
Application:
12/751,695 →
Multi-Layer Flash Memory
Patent:
8,325,528 →
Application:
12/764,054 →
Flash Memory Having Multi-Level Architecture
Charge Trap Memory Having Limited Charge Diffusion
Application:
12/764,063 →
Publication:
US 2011/0255335
Secure Memory Device Erase
Patent:
8,296,508 →
Application:
12/768,345 →
Signal Line to Indicate Program-Fail in Memory
Partitioned Bitline for Memory
Patent:
8,509,013 →
Application:
12/772,147 →
Phase Change Memory Including Ovonic Threshold Switch with Layered Electrode and Methods for Forming Same
Patent:
8,530,875 →
Application:
12/774,772 →
Forming Electrodes for Chalcogenide Containing Devices
Memory Buffer Having Accessible Information After a Program-Fail
Staggered Programming for Resistive Memories
Wordline Driver for Memory
Forming Self-Aligned Conductive Lines for Resistive Random Access Memories
Patent:
9,196,530 →
Application:
12/782,809 →
Enhanced Multilevel Memory
Persistent Memory for Processor Main Memory
Cache Coherence Protocol for Persistent Memories
Insulated Phase Change Memory
Patent:
8,530,874 →
Application:
12/828,463 →
Resistive Random Access Memory
Patent:
8,860,223 →
Application:
12/836,661 →
Write Operation for Phase Change Memory
Managed Hybrid Memory with Adaptive Power Supply
Application:
12/847,807 →
Publication:
US 2012/0026802
Forming Resistive Random Access Memories Together with Fuse Arrays
Memory Device Having Three-Dimensional Gate Structure
Modified Read Operation for Non-Volatile Memory
Phase Change Memory State Determination Using Threshold Edge Detection
Error Detection or Correction of a Portion of a Codeword in a Memory Device
Patent:
8,504,893 →
Application:
12/894,920 →
Security Protection for Memory Content of Processor Main Memory
Validating Persistent Memory Content for Processor Main Memory
Nonvolatile Storage Using Low Latency and High Latency Memory
Selective Error Control Coding in Memory Devices
Read Distribution Management for Phase Change Memory
Fabricating Bipolar Junction Select Transistors for Semiconductor Memories
Indexed Register Access for Memory Device
Metadata Storage Associated with Flash Translation Layer
Application:
12/939,953 →
Publication:
US 2012/0117303
Post Deposition Adjustment of Chalcogenide Composition in Chalcogenide Containing Semiconductors
Chalcogenide Containing Semiconductors with Chalcogenide Gradient
Charge Trap Non-Volatile Memory
Application:
12/944,125 →
Publication:
US 2012/0119280
Forming Heaters for Phase Change Memories
Method and Apparatus to Perform Concurrent Read and Write Memory Operations
Interruption of Write Memory Operations to Provide Faster Read Access in a Serial Interface Memory
Multi-Interface Memory with Access Control
Filling Cavities in Semiconductor Structures Having Adhesion Promoting Layer in the Cavities
Memory Instruction Including Parameter to Affect Operating Condition of Memory
Upwardly Tapering Heaters for Phase Change Memories
Systems and Methods for Caching Data with a Nonvolatile Memory Cache
Forming Three Dimensional Isolation Structures
Code Patching for Non-Volatile Memory
Reliable Write for Non-Volatile Memory
Application:
12/956,742 →
Publication:
US 2012/0137093
Verify or Read Pulse for Phase Change Memory and Switch
Memory Including a Selector Switch on a Variable Resistance Memory Cell
Preserving Data Integrity in a Memory System
Phase Change Memory Device with Voltage Control Elements
Memory Device Using Extended Interface Commands
Reversing a Potential Polarity for Reading Phase-Change Cells to Shorten a Recovery Delay After Programming
Programming an Array of Resistance Random Access Memory Cells Using Unipolar Pulses
Transactional Memory
Error Control in Memory Storage Systems
Reading Memory Cell History During Program Operation for Adaptive Programming
Self-Check Calibration of Program or Erase and Verify Process Using Memory Cell Distribution
Forming High Aspect Ratio Isolation Structures
Barrier Layer for Integrated Circuit Contacts
Memory Apparatus and System with Shared Wordline Decoder
Dynamic Polarization for Reducing Stress Induced Leakage Current
Reduced Signal Interface Memory Device, System, and Method
Thermal Treatment of Flash Memories
Controller to Execute Error Correcting Code Algorithms and Manage Nand Memories
Avoiding Degradation of Chalcogenide Material During Definition of Multilayer Stack Structure
Integration of Resistors and Capacitors in Charge Trap Memory Device Fabrication
Double Patterning Method for Creating a Regular Array of Pillars with Dual Shallow Trench Isolation
Method for Fabricating a Phase-Change Memory Cell
Temperature Alert and Low Rate Refresh for a Non-Volatile Memory
Wear Leveling for Erasable Memories
Memory Device and Method of Fabricating Thereof
Enhanced Addressability for Serial Non-Volatile Memory
Non-Volatile Configuration for Serial Non-Volatile Memory
Set Pulse for Phase Change Memory Programming
Reduced Voltage Nonvolatile Flash Memory
Continuous Page Read for Memory
Erase Completion Recognition
Apparatuses, Devices and Methods for Sensing a Snapback Event in a Circuit
Concurrent Memory Operations
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Aug 27, 2003
From: WILDHAGEN, JENS; SCHILL, DIETMAR
To: SONY INTERNATIONAL (EUROPE) GMBH
Reel/Frame 014427/0538 →
Merger
Jun 7, 2006
From: SONY INTERNATIONAL (EUROPE) GMBH
To: SONY DEUTSCHLAND GMBH
Reel/Frame 017746/0583 →
Assignment of Assignor's Interest
Nov 5, 2009
From: CHRISMAN, NATHAN
To: NUMONYX B.V.
Reel/Frame 023473/0288 →
Assignment of Assignor's Interest
Nov 5, 2009
From: ABDULLA, MOSTAFA NAGUIB
To: NUMONYX B.V.
Reel/Frame 023473/0276 →
Assignment of Assignor's Interest
Nov 5, 2009
From: PIAZZA, FAUSTO; MAURELLI, ALFONSO
To: NUMONYX B.V.
Reel/Frame 023473/0197 →
Assignment of Assignor's Interest
Jun 25, 2010
From: CONFALONIERI, EMANUELE; VILLA, SARA
To: NUMONYX B.V.
Reel/Frame 024597/0473 →
Assignment of Assignor's Interest
Jun 28, 2010
From: YIM, MYUNG JIN; BRAND, JASON
To: NUMONYX B.V.
Reel/Frame 024601/0579 →
Assignment of Assignor's Interest
Jun 28, 2010
From: PIROVANO, AGOSTINO; BENVENUTI, AUGUSTO; PELLIZZER, FABIO; SERVALLI, GIORGIO
To: NUMONYX B.V.
Reel/Frame 024601/0376 →
Assignment of Assignor's Interest
Jun 28, 2010
From: CONFALONIERI, EMANUELE; BALLUCHI, DANIELE; BUEB, CHRIS; MIRICHIGNI, GRAZIANO
To: NUMONYX B.V.
Reel/Frame 024601/0405 →
Assignment of Assignor's Interest
Jun 28, 2010
From: COLOMBO, ROBERTO; DI PIAZZA, LUCA
To: NUMONYX B.V.
Reel/Frame 024601/0417 →
Assignment of Assignor's Interest
Jun 28, 2010
From: LA MALFA, ANTONINO; MESSINA, MARCO
To: NUMONYX B.V.
Reel/Frame 024601/0517 →
Assignment of Assignor's Interest
Jun 28, 2010
From: VISCONTI, ANGELO; BONANOMI, MAURO; CELLERE, GIORGIO; PACCAGNELLA, ALESSANDRO
To: NUMONYX B.V.
Reel/Frame 024601/0637 →
Assignment of Assignor's Interest
Jun 28, 2010
From: GROSSI, ALESSANDRO; MARIANI, MARCELLO; CAPPELLETTI, PAOLO
To: NUMONYX B.V.
Reel/Frame 024601/0776 →
Assignment of Assignor's Interest
Jun 28, 2010
From: BUEB, CHRISTOPHER
To: NUMONYX B.V.
Reel/Frame 024602/0332 →
Assignment of Assignor's Interest
Jul 14, 2010
From: KALE, POORNA
To: NUMONYX B.V.
Reel/Frame 024685/0728 →
Assignment of Assignor's Interest
Jul 14, 2010
From: QUEVEDO, NANETTE; YIM, MYUNG JIN
To: NUMONYX B.V.
Reel/Frame 024684/0661 →
Assignment of Assignor's Interest
Jul 14, 2010
From: BARKLEY, GERALD J
To: NUMONYX B.V.
Reel/Frame 024685/0662 →
Assignment of Assignor's Interest
Jul 29, 2010
From: BARKLEY, GERALD; KALE, POORNA
To: NUMONYX B.V.
Reel/Frame 024760/0570 →
Corrective Assignment to Correct the Conveyance Document by Including the Serial Number of the Application on the Face of the Assignment Previously Recorded on Reel 024597 Frame 0473. Assignor(S) Hereby Confirms the Inclusion of Said Serial Number.
Aug 17, 2010
From: CONFALONIERI, EMANUELE; VILLA, SARA
To: NUMONYX B.V.
Reel/Frame 024856/0861 →
Assignment of Assignor's Interest
Dec 15, 2010
From: TANG, STEPHEN
To: NUMONYX B.V.
Reel/Frame 025504/0163 →
Assignment of Assignor's Interest
Oct 18, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027075/0682 →
Security Interest
May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Patent Security Agreement
Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
Assignment of Assignor's Interest
Sep 1, 2016
From: MICRON TECHNOLOGY, INC
To: OVONYX MEMORY TECHNOLOGY, LLC
Reel/Frame 039974/0496 →
Corrective Assignment to Correct the Replace Erroneously Filed Patent #7358718 with the Correct Patent #7358178 Previously Recorded on Reel 038669 Frame 0001. Assignor(S) Hereby Confirms the Security Interest.
Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →